OTP_CTRL Simulation Results

Saturday June 08 2024 00:41:57 UTC

GitHub Revision: `302b24f3c6`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 32491226968592963393132943636196950930602503490106290691157604759716956925599

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.940s	808.083us	1	1	100.00
V1	smoke	otp_ctrl_smoke	18.900s	7.357ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.410s	196.404us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.480s	686.677us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	10.290s	1.612ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.220s	1.164ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	6.100s	1.639ms	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.480s	686.677us	20	20	100.00
		otp_ctrl_csr_aliasing	6.220s	1.164ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.570s	142.408us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.420s	54.003us	5	5	100.00
V1		TOTAL			115	116	99.14
V2	dai_access_partition_walk	otp_ctrl_partition_walk	18.040s	810.612us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.070s	2.785ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	55.980s	9.437ms	10	10	100.00
		otp_ctrl_check_fail	41.810s	1.717ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	13.980s	4.215ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	2.090m	30.224ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	47.540s	3.195ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	30.250s	10.583ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	55.280s	17.164ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	54.640s	24.445ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	2.003m	15.413ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.823m	11.703ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	5.374m	39.627ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.230s	537.524us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.360s	254.862us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	6.620s	209.174us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	6.620s	209.174us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.410s	196.404us	5	5	100.00
		otp_ctrl_csr_rw	2.480s	686.677us	20	20	100.00
		otp_ctrl_csr_aliasing	6.220s	1.164ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.550s	166.833us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.410s	196.404us	5	5	100.00
		otp_ctrl_csr_rw	2.480s	686.677us	20	20	100.00
		otp_ctrl_csr_aliasing	6.220s	1.164ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.550s	166.833us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.261m	173.944ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.261m	173.944ms	5	5	100.00
		otp_ctrl_tl_intg_err	42.300s	20.157ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.261m	173.944ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.261m	173.944ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	42.300s	20.157ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	18.900s	7.357ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	18.900s	7.357ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.261m	173.944ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.261m	173.944ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.261m	173.944ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.261m	173.944ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.261m	173.944ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.261m	173.944ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.261m	173.944ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.261m	173.944ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.261m	173.944ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.261m	173.944ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.261m	173.944ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.261m	173.944ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.261m	173.944ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.261m	173.944ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.261m	173.944ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	55.280s	17.164ms	200	200	100.00
		otp_ctrl_sec_cm	4.261m	173.944ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	55.280s	17.164ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	55.280s	17.164ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	55.280s	17.164ms	200	200	100.00
		otp_ctrl_macro_errs	2.003m	15.413ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	55.280s	17.164ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	55.280s	17.164ms	200	200	100.00
		otp_ctrl_sec_cm	4.261m	173.944ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	55.280s	17.164ms	200	200	100.00
		otp_ctrl_sec_cm	4.261m	173.944ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	55.280s	17.164ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	55.280s	17.164ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	55.280s	17.164ms	200	200	100.00
		otp_ctrl_macro_errs	2.003m	15.413ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	55.280s	17.164ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	55.280s	17.164ms	200	200	100.00
		otp_ctrl_sec_cm	4.261m	173.944ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.070s	2.785ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	41.810s	1.717ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	2.090m	30.224ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	2.090m	30.224ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	2.090m	30.224ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	2.090m	30.224ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	2.090m	30.224ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	18.900s	7.357ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	2.090m	30.224ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	18.900s	7.357ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.261m	173.944ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	13.980s	4.215ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	18.900s	7.357ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	18.900s	7.357ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	2.003m	15.413ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	13.660s	5.876ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.506h	1.293s	78	100	78.00
V3		TOTAL			79	101	78.22
		TOTAL			1320	1343	98.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.90	93.89	96.18	95.94	91.65	97.05	96.33	93.28

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 12 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 12 failures.
  - 3.otp_ctrl_stress_all_with_rand_reset.79739349163789632958639186100101501035454941599436873968461711547619646617343
    Line 114641, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 723656565119 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 723656565119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.otp_ctrl_stress_all_with_rand_reset.111004013983625327031854850493628644432220781498964608530752099270393813188590
    Line 72916, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 27569184503 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 27569184503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 5 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 5 failures.
  - 33.otp_ctrl_stress_all_with_rand_reset.88206913420471001036065940670280606594458103030799777077945889761074489470738
    Line 57308, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8492039032 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2924287581 [0xae4d165d] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 8492039032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 50.otp_ctrl_stress_all_with_rand_reset.115789291448533583370092940413717309821840719171736769398823475717486671465130
    Line 7636, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/50.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 224872127241 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3855035004 [0xe5c72a7c] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 224872127241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
Offending '(cio_test_en_o == *)' has 3 failures:
- Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 3.otp_ctrl_csr_mem_rw_with_rand_reset.111376555975431302265670119966086740974171403099495694396331730893054967675424
    Line 267, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 105629797 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 105629797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 85.otp_ctrl_stress_all_with_rand_reset.65216088834173783771108360283254303736396224906852796170017609983419219962255
    Line 9991, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/85.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 433349923717 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 433349923717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 99.otp_ctrl_stress_all_with_rand_reset.95967608703283911753983106147305661178090554860487929935552470988435148136178
    Line 46131, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/99.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 48133321903 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 48133321903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

4.otp_ctrl_stress_all_with_rand_reset.107339842724611777185682871073203786979831669484175608194442436416812632465319
Line 51391, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 9330018276 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 9330331407 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 9330351609 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 9331634436 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 9331705143 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 48.otp_ctrl_stress_all_with_rand_reset.35173939602234962812461321241598778305386984527238670495043829264415652986336
    Line 34450, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 23783904188 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 23783904188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 52.otp_ctrl_stress_all_with_rand_reset.89544833802680582241955959771058564695568533283463646319150279872939095838834
    Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/52.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3044667411 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1684 [0x694]) dai addr 694 rdata0 readout mismatch
  UVM_INFO @ 3044667411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```