OTP_CTRL Simulation Results

Sunday June 09 2024 19:02:32 UTC

GitHub Revision: f92a5ee77b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 74888572473032497941251936200792687439223302665780333354656685678472336958420

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.700s	103.130us	1	1	100.00
V1	smoke	otp_ctrl_smoke	15.130s	6.557ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.560s	140.295us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.400s	573.862us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	12.030s	6.806ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	5.960s	1.528ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	5.310s	1.671ms	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.400s	573.862us	20	20	100.00
		otp_ctrl_csr_aliasing	5.960s	1.528ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	2.000s	530.011us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.730s	519.076us	5	5	100.00
V1		TOTAL			115	116	99.14
V2	dai_access_partition_walk	otp_ctrl_partition_walk	25.200s	5.056ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.770s	2.474ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	32.830s	950.240us	10	10	100.00
		otp_ctrl_check_fail	52.730s	13.509ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	12.920s	327.343us	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	45.030s	21.401ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.074m	25.224ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	32.600s	8.792ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	57.970s	17.104ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	51.810s	14.223ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.747m	9.321ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	49.020s	3.084ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	5.040m	22.909ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.190s	612.476us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.860s	1.067ms	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	10.150s	3.081ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	10.150s	3.081ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.560s	140.295us	5	5	100.00
		otp_ctrl_csr_rw	2.400s	573.862us	20	20	100.00
		otp_ctrl_csr_aliasing	5.960s	1.528ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.570s	1.245ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.560s	140.295us	5	5	100.00
		otp_ctrl_csr_rw	2.400s	573.862us	20	20	100.00
		otp_ctrl_csr_aliasing	5.960s	1.528ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.570s	1.245ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	6.389m	165.253ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	6.389m	165.253ms	5	5	100.00
		otp_ctrl_tl_intg_err	43.610s	20.047ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	6.389m	165.253ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	6.389m	165.253ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	43.610s	20.047ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	15.130s	6.557ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	15.130s	6.557ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	6.389m	165.253ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	6.389m	165.253ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	6.389m	165.253ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	6.389m	165.253ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	6.389m	165.253ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	6.389m	165.253ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	6.389m	165.253ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	6.389m	165.253ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	6.389m	165.253ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	6.389m	165.253ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	6.389m	165.253ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	6.389m	165.253ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	6.389m	165.253ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	6.389m	165.253ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	6.389m	165.253ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	57.970s	17.104ms	200	200	100.00
		otp_ctrl_sec_cm	6.389m	165.253ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	57.970s	17.104ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	57.970s	17.104ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	57.970s	17.104ms	200	200	100.00
		otp_ctrl_macro_errs	1.747m	9.321ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	57.970s	17.104ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	57.970s	17.104ms	200	200	100.00
		otp_ctrl_sec_cm	6.389m	165.253ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	57.970s	17.104ms	200	200	100.00
		otp_ctrl_sec_cm	6.389m	165.253ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	57.970s	17.104ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	57.970s	17.104ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	57.970s	17.104ms	200	200	100.00
		otp_ctrl_macro_errs	1.747m	9.321ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	57.970s	17.104ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	57.970s	17.104ms	200	200	100.00
		otp_ctrl_sec_cm	6.389m	165.253ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.770s	2.474ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	52.730s	13.509ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	45.030s	21.401ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	45.030s	21.401ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	45.030s	21.401ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	45.030s	21.401ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	45.030s	21.401ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	15.130s	6.557ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	45.030s	21.401ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	15.130s	6.557ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	6.389m	165.253ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	12.920s	327.343us	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	15.130s	6.557ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	15.130s	6.557ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.747m	9.321ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	14.390s	3.411ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.377h	643.238ms	84	100	84.00
V3		TOTAL			85	101	84.16
		TOTAL			1326	1343	98.73

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.88	93.89	96.30	95.53	91.65	97.10	96.33	93.35

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 8 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 8 failures.

    • 9.otp_ctrl_stress_all_with_rand_reset.58500578149545438599588692101361434079896189784003843138836924817688223171430
      Line 88855, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 502696738982 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 502696738982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 22.otp_ctrl_stress_all_with_rand_reset.104696107962762379449581053249802305042510871259461790447252075879524152844175
      Line 39985, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 25387198564 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 25387198564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 6 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 7 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 7 failures.

    • 7.otp_ctrl_stress_all_with_rand_reset.106025079081052600288768620603282856746168722803176275312937801164088797506509
      Line 15096, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 69146480258 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3769270247 [0xe0aa7fe7] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 69146480258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 13.otp_ctrl_stress_all_with_rand_reset.16822119256669015265166751710491013013663205675152083738347221633407689965770
      Line 1310, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 302620905229 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1115441400 [0x427c48f8] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 302620905229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• Offending '(cio_test_en_o == *)' has 2 failures:

  • Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 1.otp_ctrl_csr_mem_rw_with_rand_reset.2281313244446870041846149770561931752189274789775169160288407989601741985164
      Line 276, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @  59856932 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @  59856932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 41.otp_ctrl_stress_all_with_rand_reset.115142262724542807775558924876061121388079826662655421457382872677995039745585
      Line 46690, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 61806116569 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 61806116569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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