OTP_CTRL Simulation Results

Monday June 10 2024 23:28:43 UTC

GitHub Revision: `a8c9c17a8c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 72227341233107832543509484606850665418885932500709631655793413524197290927900

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.740s	103.771us	1	1	100.00
V1	smoke	otp_ctrl_smoke	14.470s	1.259ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	3.050s	1.046ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.990s	605.715us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	11.350s	933.786us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	5.870s	156.898us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	7.170s	1.693ms	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.990s	605.715us	20	20	100.00
		otp_ctrl_csr_aliasing	5.870s	156.898us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.420s	48.840us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.960s	519.000us	5	5	100.00
V1		TOTAL			115	116	99.14
V2	dai_access_partition_walk	otp_ctrl_partition_walk	18.760s	784.426us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	7.570s	1.921ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	42.790s	23.797ms	10	10	100.00
		otp_ctrl_check_fail	46.750s	20.053ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	16.670s	4.515ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	52.460s	8.627ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	48.340s	2.197ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	34.950s	13.644ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	38.750s	13.637ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	52.700s	5.927ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.277m	34.490ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.120m	9.351ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	6.439m	84.232ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.100s	513.940us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.160s	235.429us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	6.250s	180.389us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	6.250s	180.389us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	3.050s	1.046ms	5	5	100.00
		otp_ctrl_csr_rw	1.990s	605.715us	20	20	100.00
		otp_ctrl_csr_aliasing	5.870s	156.898us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.620s	1.656ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	3.050s	1.046ms	5	5	100.00
		otp_ctrl_csr_rw	1.990s	605.715us	20	20	100.00
		otp_ctrl_csr_aliasing	5.870s	156.898us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.620s	1.656ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.487m	38.774ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.487m	38.774ms	5	5	100.00
		otp_ctrl_tl_intg_err	23.650s	4.569ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.487m	38.774ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.487m	38.774ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	23.650s	4.569ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	14.470s	1.259ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	14.470s	1.259ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.487m	38.774ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.487m	38.774ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.487m	38.774ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.487m	38.774ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.487m	38.774ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.487m	38.774ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.487m	38.774ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.487m	38.774ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.487m	38.774ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.487m	38.774ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.487m	38.774ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.487m	38.774ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.487m	38.774ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.487m	38.774ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.487m	38.774ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	38.750s	13.637ms	200	200	100.00
		otp_ctrl_sec_cm	3.487m	38.774ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	38.750s	13.637ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	38.750s	13.637ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	38.750s	13.637ms	200	200	100.00
		otp_ctrl_macro_errs	1.277m	34.490ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	38.750s	13.637ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	38.750s	13.637ms	200	200	100.00
		otp_ctrl_sec_cm	3.487m	38.774ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	38.750s	13.637ms	200	200	100.00
		otp_ctrl_sec_cm	3.487m	38.774ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	38.750s	13.637ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	38.750s	13.637ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	38.750s	13.637ms	200	200	100.00
		otp_ctrl_macro_errs	1.277m	34.490ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	38.750s	13.637ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	38.750s	13.637ms	200	200	100.00
		otp_ctrl_sec_cm	3.487m	38.774ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	7.570s	1.921ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	46.750s	20.053ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	52.460s	8.627ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	52.460s	8.627ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	52.460s	8.627ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	52.460s	8.627ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	52.460s	8.627ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	14.470s	1.259ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	52.460s	8.627ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	14.470s	1.259ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.487m	38.774ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	16.670s	4.515ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	14.470s	1.259ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	14.470s	1.259ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.277m	34.490ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.010s	3.393ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.160h	519.367ms	79	100	79.00
V3		TOTAL			80	101	79.21
		TOTAL			1321	1343	98.36

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.08	93.89	96.62	96.07	92.12	97.24	96.33	93.28

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 9 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 9 failures.
  - 17.otp_ctrl_stress_all_with_rand_reset.54670410595540473065749074003985400479432835812579770818137202314548588098131
    Line 103512, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 119709370138 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 119709370138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.otp_ctrl_stress_all_with_rand_reset.43803524372413337278031304576488571535162938335975361534735868640140599870955
    Line 575, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1159520712 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 1159520712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 7 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 7 failures.
  - 33.otp_ctrl_stress_all_with_rand_reset.48062387359988181236087516686543330000293575098760165312038411845533115594403
    Line 44620, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1009664429457 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2163042930 [0x80ed6a72] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 1009664429457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 41.otp_ctrl_stress_all_with_rand_reset.26239945362793005112464852166900853577951393699733182428890623656612700071083
    Line 21958, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 40878668330 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2296221204 [0x88dd8e14] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 40878668330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
Offending '(cio_test_en_o == *)' has 2 failures:
- Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 13.otp_ctrl_csr_mem_rw_with_rand_reset.13684671284838390349409014589278551021189699767084677974250233031312222578686
    Line 267, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  28085765 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  28085765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 83.otp_ctrl_stress_all_with_rand_reset.54840041101393361969109473376844329928743668381823728067749173044700254260419
    Line 89548, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/83.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 318360227473 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 318360227473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 2 failures:

Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

52.otp_ctrl_stress_all_with_rand_reset.30045264824811258396144511823658646973493592615286218709444624680061076658104
Line 48345, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/52.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 8559376429 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 8559407680 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 8559636854 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 8559678522 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 8559678522 ps: (dv_base_reg.sv:325) [otp_ctrl_core_reg_block.direct_access_regwen] lock_lockable_flds          1 val

60.otp_ctrl_stress_all_with_rand_reset.65635240484553330515581815146858553759847219306477050459580038298647629467145
Line 32956, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/60.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 71693910686 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 71693950686 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 71696990686 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 71697190686 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 71698470686 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 3.otp_ctrl_stress_all_with_rand_reset.15649882332740044973872572413236695725208756842666896100383817522028855627702
    Line 272, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12650313027 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 266265943 [0xfdee557]) dai addr 740 rdata0 readout mismatch
  UVM_INFO @ 12650313027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 91.otp_ctrl_stress_all_with_rand_reset.114466716392763552584836438298706431506699167408149285614205750172897468753361
    Line 47597, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/91.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 258729585579 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 258729585579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```