OTP_CTRL Simulation Results

Tuesday June 11 2024 19:02:38 UTC

GitHub Revision: dd5ad5fb77

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 66418170746903624595625818392428707033482455256751560525176982524210226376736

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 wake_up otp_ctrl_wake_up 1.680s 66.494us 1 1 100.00
V1 smoke otp_ctrl_smoke 19.790s 6.581ms 50 50 100.00
V1 csr_hw_reset otp_ctrl_csr_hw_reset 3.400s 1.605ms 5 5 100.00
V1 csr_rw otp_ctrl_csr_rw 2.010s 656.848us 20 20 100.00
V1 csr_bit_bash otp_ctrl_csr_bit_bash 6.250s 127.083us 5 5 100.00
V1 csr_aliasing otp_ctrl_csr_aliasing 6.540s 200.523us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otp_ctrl_csr_mem_rw_with_rand_reset 6.000s 1.630ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr otp_ctrl_csr_rw 2.010s 656.848us 20 20 100.00
otp_ctrl_csr_aliasing 6.540s 200.523us 5 5 100.00
V1 mem_walk otp_ctrl_mem_walk 1.990s 527.644us 5 5 100.00
V1 mem_partial_access otp_ctrl_mem_partial_access 1.560s 131.450us 5 5 100.00
V1 TOTAL 116 116 100.00
V2 dai_access_partition_walk otp_ctrl_partition_walk 19.260s 1.228ms 1 1 100.00
V2 init_fail otp_ctrl_init_fail 8.750s 2.597ms 300 300 100.00
V2 partition_check otp_ctrl_background_chks 1.099m 7.210ms 10 10 100.00
otp_ctrl_check_fail 48.080s 17.102ms 50 50 100.00
V2 regwen_during_otp_init otp_ctrl_regwen 17.740s 4.927ms 50 50 100.00
V2 partition_lock otp_ctrl_dai_lock 54.680s 26.715ms 50 50 100.00
V2 interface_key_check otp_ctrl_parallel_key_req 49.800s 20.360ms 50 50 100.00
V2 lc_interactions otp_ctrl_parallel_lc_req 45.730s 13.169ms 50 50 100.00
otp_ctrl_parallel_lc_esc 33.140s 3.566ms 200 200 100.00
V2 otp_dai_errors otp_ctrl_dai_errs 53.890s 20.622ms 50 50 100.00
V2 otp_macro_errors otp_ctrl_macro_errs 1.202m 4.708ms 50 50 100.00
V2 test_access otp_ctrl_test_access 2.791m 29.842ms 50 50 100.00
V2 stress_all otp_ctrl_stress_all 6.914m 32.162ms 50 50 100.00
V2 intr_test otp_ctrl_intr_test 2.050s 560.858us 50 50 100.00
V2 alert_test otp_ctrl_alert_test 3.360s 1.069ms 50 50 100.00
V2 tl_d_oob_addr_access otp_ctrl_tl_errors 8.140s 3.030ms 20 20 100.00
V2 tl_d_illegal_access otp_ctrl_tl_errors 8.140s 3.030ms 20 20 100.00
V2 tl_d_outstanding_access otp_ctrl_csr_hw_reset 3.400s 1.605ms 5 5 100.00
otp_ctrl_csr_rw 2.010s 656.848us 20 20 100.00
otp_ctrl_csr_aliasing 6.540s 200.523us 5 5 100.00
otp_ctrl_same_csr_outstanding 3.630s 142.033us 20 20 100.00
V2 tl_d_partial_access otp_ctrl_csr_hw_reset 3.400s 1.605ms 5 5 100.00
otp_ctrl_csr_rw 2.010s 656.848us 20 20 100.00
otp_ctrl_csr_aliasing 6.540s 200.523us 5 5 100.00
otp_ctrl_same_csr_outstanding 3.630s 142.033us 20 20 100.00
V2 TOTAL 1101 1101 100.00
V2S sec_cm_additional_check otp_ctrl_sec_cm 3.472m 14.841ms 5 5 100.00
V2S tl_intg_err otp_ctrl_sec_cm 3.472m 14.841ms 5 5 100.00
otp_ctrl_tl_intg_err 35.780s 20.132ms 20 20 100.00
V2S prim_count_check otp_ctrl_sec_cm 3.472m 14.841ms 5 5 100.00
V2S prim_fsm_check otp_ctrl_sec_cm 3.472m 14.841ms 5 5 100.00
V2S sec_cm_bus_integrity otp_ctrl_tl_intg_err 35.780s 20.132ms 20 20 100.00
V2S sec_cm_secret_mem_scramble otp_ctrl_smoke 19.790s 6.581ms 50 50 100.00
V2S sec_cm_part_mem_digest otp_ctrl_smoke 19.790s 6.581ms 50 50 100.00
V2S sec_cm_dai_fsm_sparse otp_ctrl_sec_cm 3.472m 14.841ms 5 5 100.00
V2S sec_cm_kdi_fsm_sparse otp_ctrl_sec_cm 3.472m 14.841ms 5 5 100.00
V2S sec_cm_lci_fsm_sparse otp_ctrl_sec_cm 3.472m 14.841ms 5 5 100.00
V2S sec_cm_part_fsm_sparse otp_ctrl_sec_cm 3.472m 14.841ms 5 5 100.00
V2S sec_cm_scrmbl_fsm_sparse otp_ctrl_sec_cm 3.472m 14.841ms 5 5 100.00
V2S sec_cm_timer_fsm_sparse otp_ctrl_sec_cm 3.472m 14.841ms 5 5 100.00
V2S sec_cm_dai_ctr_redun otp_ctrl_sec_cm 3.472m 14.841ms 5 5 100.00
V2S sec_cm_kdi_seed_ctr_redun otp_ctrl_sec_cm 3.472m 14.841ms 5 5 100.00
V2S sec_cm_kdi_entropy_ctr_redun otp_ctrl_sec_cm 3.472m 14.841ms 5 5 100.00
V2S sec_cm_lci_ctr_redun otp_ctrl_sec_cm 3.472m 14.841ms 5 5 100.00
V2S sec_cm_part_ctr_redun otp_ctrl_sec_cm 3.472m 14.841ms 5 5 100.00
V2S sec_cm_scrmbl_ctr_redun otp_ctrl_sec_cm 3.472m 14.841ms 5 5 100.00
V2S sec_cm_timer_integ_ctr_redun otp_ctrl_sec_cm 3.472m 14.841ms 5 5 100.00
V2S sec_cm_timer_cnsty_ctr_redun otp_ctrl_sec_cm 3.472m 14.841ms 5 5 100.00
V2S sec_cm_timer_lfsr_redun otp_ctrl_sec_cm 3.472m 14.841ms 5 5 100.00
V2S sec_cm_dai_fsm_local_esc otp_ctrl_parallel_lc_esc 33.140s 3.566ms 200 200 100.00
otp_ctrl_sec_cm 3.472m 14.841ms 5 5 100.00
V2S sec_cm_lci_fsm_local_esc otp_ctrl_parallel_lc_esc 33.140s 3.566ms 200 200 100.00
V2S sec_cm_kdi_fsm_local_esc otp_ctrl_parallel_lc_esc 33.140s 3.566ms 200 200 100.00
V2S sec_cm_part_fsm_local_esc otp_ctrl_parallel_lc_esc 33.140s 3.566ms 200 200 100.00
otp_ctrl_macro_errs 1.202m 4.708ms 50 50 100.00
V2S sec_cm_scrmbl_fsm_local_esc otp_ctrl_parallel_lc_esc 33.140s 3.566ms 200 200 100.00
V2S sec_cm_timer_fsm_local_esc otp_ctrl_parallel_lc_esc 33.140s 3.566ms 200 200 100.00
otp_ctrl_sec_cm 3.472m 14.841ms 5 5 100.00
V2S sec_cm_dai_fsm_global_esc otp_ctrl_parallel_lc_esc 33.140s 3.566ms 200 200 100.00
otp_ctrl_sec_cm 3.472m 14.841ms 5 5 100.00
V2S sec_cm_lci_fsm_global_esc otp_ctrl_parallel_lc_esc 33.140s 3.566ms 200 200 100.00
V2S sec_cm_kdi_fsm_global_esc otp_ctrl_parallel_lc_esc 33.140s 3.566ms 200 200 100.00
V2S sec_cm_part_fsm_global_esc otp_ctrl_parallel_lc_esc 33.140s 3.566ms 200 200 100.00
otp_ctrl_macro_errs 1.202m 4.708ms 50 50 100.00
V2S sec_cm_scrmbl_fsm_global_esc otp_ctrl_parallel_lc_esc 33.140s 3.566ms 200 200 100.00
V2S sec_cm_timer_fsm_global_esc otp_ctrl_parallel_lc_esc 33.140s 3.566ms 200 200 100.00
otp_ctrl_sec_cm 3.472m 14.841ms 5 5 100.00
V2S sec_cm_part_data_reg_integrity otp_ctrl_init_fail 8.750s 2.597ms 300 300 100.00
V2S sec_cm_part_data_reg_bkgn_chk otp_ctrl_check_fail 48.080s 17.102ms 50 50 100.00
V2S sec_cm_part_mem_regren otp_ctrl_dai_lock 54.680s 26.715ms 50 50 100.00
V2S sec_cm_part_mem_sw_unreadable otp_ctrl_dai_lock 54.680s 26.715ms 50 50 100.00
V2S sec_cm_part_mem_sw_unwritable otp_ctrl_dai_lock 54.680s 26.715ms 50 50 100.00
V2S sec_cm_lc_part_mem_sw_noaccess otp_ctrl_dai_lock 54.680s 26.715ms 50 50 100.00
V2S sec_cm_access_ctrl_mubi otp_ctrl_dai_lock 54.680s 26.715ms 50 50 100.00
V2S sec_cm_token_valid_ctrl_mubi otp_ctrl_smoke 19.790s 6.581ms 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi otp_ctrl_dai_lock 54.680s 26.715ms 50 50 100.00
V2S sec_cm_test_bus_lc_gated otp_ctrl_smoke 19.790s 6.581ms 50 50 100.00
V2S sec_cm_test_tl_lc_gate_fsm_sparse otp_ctrl_sec_cm 3.472m 14.841ms 5 5 100.00
V2S sec_cm_direct_access_config_regwen otp_ctrl_regwen 17.740s 4.927ms 50 50 100.00
V2S sec_cm_check_trigger_config_regwen otp_ctrl_smoke 19.790s 6.581ms 50 50 100.00
V2S sec_cm_check_config_regwen otp_ctrl_smoke 19.790s 6.581ms 50 50 100.00
V2S sec_cm_macro_mem_integrity otp_ctrl_macro_errs 1.202m 4.708ms 50 50 100.00
V2S TOTAL 25 25 100.00
V3 otp_ctrl_low_freq_read otp_ctrl_low_freq_read 12.220s 3.057ms 1 1 100.00
V3 stress_all_with_rand_reset otp_ctrl_stress_all_with_rand_reset 58.980m 144.434ms 85 100 85.00
V3 TOTAL 86 101 85.15
TOTAL 1328 1343 98.88

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 17 17 17 100.00
V2S 2 2 2 100.00
V3 2 2 1 50.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.09 93.87 96.65 95.85 92.36 97.24 96.33 93.35

Failure Buckets

Past Results