OTP_CTRL Simulation Results

Thursday June 13 2024 19:02:12 UTC

GitHub Revision: `548a3880d8`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 95435389850697596633112362018639443702533575559488568730544091582583938649085

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.860s	100.254us	1	1	100.00
V1	smoke	otp_ctrl_smoke	12.360s	546.858us	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.730s	193.807us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.190s	622.065us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	8.340s	612.953us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.180s	202.165us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.300s	210.447us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.190s	622.065us	20	20	100.00
		otp_ctrl_csr_aliasing	6.180s	202.165us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.390s	70.777us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.570s	534.269us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	18.390s	953.932us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.750s	2.026ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	3.682m	29.906ms	10	10	100.00
		otp_ctrl_check_fail	41.770s	19.998ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	19.640s	4.476ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	38.950s	11.739ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.611m	4.769ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	39.750s	11.056ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	41.580s	12.975ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	44.740s	4.987ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	59.660s	8.543ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.007m	11.235ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	7.211m	45.552ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.080s	518.362us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.930s	803.106us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	8.860s	418.977us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	8.860s	418.977us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.730s	193.807us	5	5	100.00
		otp_ctrl_csr_rw	2.190s	622.065us	20	20	100.00
		otp_ctrl_csr_aliasing	6.180s	202.165us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.620s	453.903us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.730s	193.807us	5	5	100.00
		otp_ctrl_csr_rw	2.190s	622.065us	20	20	100.00
		otp_ctrl_csr_aliasing	6.180s	202.165us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.620s	453.903us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.553m	11.084ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.553m	11.084ms	5	5	100.00
		otp_ctrl_tl_intg_err	22.400s	10.391ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.553m	11.084ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.553m	11.084ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	22.400s	10.391ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	12.360s	546.858us	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	12.360s	546.858us	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.553m	11.084ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.553m	11.084ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.553m	11.084ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.553m	11.084ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.553m	11.084ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.553m	11.084ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.553m	11.084ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.553m	11.084ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.553m	11.084ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.553m	11.084ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.553m	11.084ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.553m	11.084ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.553m	11.084ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.553m	11.084ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.553m	11.084ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.580s	12.975ms	200	200	100.00
		otp_ctrl_sec_cm	3.553m	11.084ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.580s	12.975ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.580s	12.975ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.580s	12.975ms	200	200	100.00
		otp_ctrl_macro_errs	59.660s	8.543ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.580s	12.975ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.580s	12.975ms	200	200	100.00
		otp_ctrl_sec_cm	3.553m	11.084ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.580s	12.975ms	200	200	100.00
		otp_ctrl_sec_cm	3.553m	11.084ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.580s	12.975ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.580s	12.975ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.580s	12.975ms	200	200	100.00
		otp_ctrl_macro_errs	59.660s	8.543ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.580s	12.975ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.580s	12.975ms	200	200	100.00
		otp_ctrl_sec_cm	3.553m	11.084ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.750s	2.026ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	41.770s	19.998ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	38.950s	11.739ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	38.950s	11.739ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	38.950s	11.739ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	38.950s	11.739ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	38.950s	11.739ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	12.360s	546.858us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	38.950s	11.739ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	12.360s	546.858us	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.553m	11.084ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	19.640s	4.476ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	12.360s	546.858us	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	12.360s	546.858us	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	59.660s	8.543ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	16.110s	3.063ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	56.303m	142.946ms	82	100	82.00
V3		TOTAL			83	101	82.18
		TOTAL			1325	1343	98.66

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 9 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 9 failures.
  - 19.otp_ctrl_stress_all_with_rand_reset.92079991181225298704794590052935429162470906162129477813976156922315435495975
    Line 1900, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 85796504807 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 85796504807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.otp_ctrl_stress_all_with_rand_reset.44791886809523932072667286567010108342894877915946152381409227116031460935757
    Line 9305, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1880635108 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 1880635108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 5 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 5 failures.
  - 39.otp_ctrl_stress_all_with_rand_reset.92571016319710229716359658618683826820471891633011187474907198489976403750159
    Line 52726, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 243366431496 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (811942025 [0x30654089] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 243366431496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.otp_ctrl_stress_all_with_rand_reset.40557175587381022526551263196680812397322433633903241849238146598250434669980
    Line 330, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  78276227 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3772561589 [0xe0dcb8b5] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @  78276227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

47.otp_ctrl_stress_all_with_rand_reset.111516946754928630228598531082229254455169759336855742756656052160874182737363
Line 66310, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 62680848710 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 62681432034 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 62681452867 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 62682327853 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 62682348686 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 49.otp_ctrl_stress_all_with_rand_reset.42776919223143399873150709929251320610568139247858723381371881720352081190839
    Line 12521, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13281144534 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1560 [0x618]) dai addr 618 rdata0 readout mismatch
  UVM_INFO @ 13281144534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:752) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 82.otp_ctrl_stress_all_with_rand_reset.54122391845139454483557677698111645544246823970597775791885684730489240433948
    Line 4233, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/82.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 166329714832 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 166329714832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(cio_test_en_o == *)' has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 91.otp_ctrl_stress_all_with_rand_reset.398252656000564856643597286139696283212845271172104107437150704667480945399
    Line 3342, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/91.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 4217016647 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 4217016647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unauthenticated desc = transport: oauth2: cannot fetch token: * Bad Request Response: {"error":"invalid_grant","error_description":"Invalid JWT Signature."} has 1 failures:
- Test otp_ctrl has 1 failures.
  - cov_merge
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/cov_merge/merged.vdb/cov_merge.log
Job killed most likely because its dependent job failed. has 1 failures:
- Test otp_ctrl has 1 failures.
  - cov_report
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/cov_report/cov_report.log