OTP_CTRL Simulation Results

Friday June 21 2024 23:02:45 UTC

GitHub Revision: `de38ce313c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 40294666978553523170681160506532247841705182588034413483474981853853670477454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.740s	69.824us	1	1	100.00
V1	smoke	otp_ctrl_smoke	33.010s	9.219ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	4.760s	1.514ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.920s	644.283us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	7.030s	1.983ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.490s	619.061us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	3.910s	400.636us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.920s	644.283us	20	20	100.00
		otp_ctrl_csr_aliasing	6.490s	619.061us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.470s	531.654us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.470s	526.192us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	28.870s	12.800ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.500s	2.966ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	42.230s	4.815ms	10	10	100.00
		otp_ctrl_check_fail	48.740s	24.688ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	13.110s	4.421ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.975m	26.632ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	57.060s	25.033ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	29.720s	11.135ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	35.590s	14.906ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	47.440s	5.984ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.821m	24.379ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.334m	17.265ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	12.910m	70.815ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.060s	519.495us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.370s	252.328us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	6.660s	397.426us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	6.660s	397.426us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	4.760s	1.514ms	5	5	100.00
		otp_ctrl_csr_rw	1.920s	644.283us	20	20	100.00
		otp_ctrl_csr_aliasing	6.490s	619.061us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.840s	1.674ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	4.760s	1.514ms	5	5	100.00
		otp_ctrl_csr_rw	1.920s	644.283us	20	20	100.00
		otp_ctrl_csr_aliasing	6.490s	619.061us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.840s	1.674ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	5.939m	165.428ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	5.939m	165.428ms	5	5	100.00
		otp_ctrl_tl_intg_err	27.570s	20.108ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	5.939m	165.428ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	5.939m	165.428ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	27.570s	20.108ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	33.010s	9.219ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	33.010s	9.219ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	5.939m	165.428ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	5.939m	165.428ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	5.939m	165.428ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	5.939m	165.428ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	5.939m	165.428ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	5.939m	165.428ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	5.939m	165.428ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	5.939m	165.428ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	5.939m	165.428ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	5.939m	165.428ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	5.939m	165.428ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	5.939m	165.428ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	5.939m	165.428ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	5.939m	165.428ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	5.939m	165.428ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	35.590s	14.906ms	200	200	100.00
		otp_ctrl_sec_cm	5.939m	165.428ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	35.590s	14.906ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	35.590s	14.906ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	35.590s	14.906ms	200	200	100.00
		otp_ctrl_macro_errs	1.821m	24.379ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	35.590s	14.906ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	35.590s	14.906ms	200	200	100.00
		otp_ctrl_sec_cm	5.939m	165.428ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	35.590s	14.906ms	200	200	100.00
		otp_ctrl_sec_cm	5.939m	165.428ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	35.590s	14.906ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	35.590s	14.906ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	35.590s	14.906ms	200	200	100.00
		otp_ctrl_macro_errs	1.821m	24.379ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	35.590s	14.906ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	35.590s	14.906ms	200	200	100.00
		otp_ctrl_sec_cm	5.939m	165.428ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.500s	2.966ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	48.740s	24.688ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.975m	26.632ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.975m	26.632ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.975m	26.632ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.975m	26.632ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.975m	26.632ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	33.010s	9.219ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.975m	26.632ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	33.010s	9.219ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	5.939m	165.428ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	13.110s	4.421ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	33.010s	9.219ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	33.010s	9.219ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.821m	24.379ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	16.010s	3.084ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	57.938m	135.351ms	79	100	79.00
V3		TOTAL			80	101	79.21
		TOTAL			1322	1343	98.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.95	93.81	96.15	95.58	92.36	97.05	96.34	93.35

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 8 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 8 failures.
  - 0.otp_ctrl_stress_all_with_rand_reset.96647217580960847852721757742707943364490684194855475398012799836849327581017
    Line 16761, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6299132149 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 6299132149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.otp_ctrl_stress_all_with_rand_reset.39060936074247716910874226032099451675340741691565009575966806184278564189226
    Line 46298, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 175450592215 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 175450592215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 6 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 6 failures.
  - 17.otp_ctrl_stress_all_with_rand_reset.102399409819632456722952436559139415357674380547066168153924448592212874858323
    Line 27705, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 161137771048 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1088681354 [0x40e3f58a] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 161137771048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 34.otp_ctrl_stress_all_with_rand_reset.74196058560996323660644202936783897601941259019507282865650582586581491172027
    Line 18822, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 110433643249 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3199965401 [0xbebb98d9] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 110433643249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Offending '(cio_test_en_o == *)' has 4 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 4 failures.
  - 2.otp_ctrl_stress_all_with_rand_reset.37459127247167686361753087059895697820360721869866600029610082820878334118312
    Line 14175, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 51841672580 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 51841672580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 48.otp_ctrl_stress_all_with_rand_reset.75208830681484100677012275506321242364331341239467168484439934412607976359066
    Line 11287, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 1567773096 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 1567773096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 2 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:277) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 23.otp_ctrl_stress_all_with_rand_reset.94640656543611830048765440162679664215855958442214559771522443979579611893851
    Line 29771, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 47727262891 ps: (otp_ctrl_scoreboard.sv:277) [uvm_test_top.env.scoreboard] Check failed exp_alert != OtpNoAlert (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 47727262891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

26.otp_ctrl_stress_all_with_rand_reset.61799920565449922617676577120995935864200369833993628385192696130460503186648
Line 4877, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 16680596805 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 16680656805 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 16681136805 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 16681276805 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 16681656805 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *a* rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 53.otp_ctrl_stress_all_with_rand_reset.32621236731134697556047902122140305317446008814199849418853675690485138397108
    Line 25450, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/53.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 232325649673 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1444 [0x5a4]) dai addr 5a4 rdata0 readout mismatch
  UVM_INFO @ 232325649673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```