OTP_CTRL Simulation Results

Saturday June 22 2024 23:02:20 UTC

GitHub Revision: `8fdb25c8d9`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 116774179587740886356693500529232784059703555433764635649168222249757162669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.880s	99.211us	1	1	100.00
V1	smoke	otp_ctrl_smoke	17.000s	4.822ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.380s	395.394us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.970s	624.072us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	11.510s	2.050ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	5.010s	132.990us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.640s	1.647ms	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.970s	624.072us	20	20	100.00
		otp_ctrl_csr_aliasing	5.010s	132.990us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.630s	506.628us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.440s	140.053us	5	5	100.00
V1		TOTAL			115	116	99.14
V2	dai_access_partition_walk	otp_ctrl_partition_walk	20.240s	1.480ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.960s	2.381ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	32.310s	7.186ms	10	10	100.00
		otp_ctrl_check_fail	1.236m	9.022ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	15.720s	4.485ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	52.530s	15.458ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	51.370s	6.665ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	45.140s	12.718ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	44.170s	13.857ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.136m	22.513ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.167m	6.223ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	56.520s	10.819ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	7.543m	165.294ms	49	50	98.00
V2	intr_test	otp_ctrl_intr_test	1.900s	535.485us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.980s	739.672us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.090s	285.303us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.090s	285.303us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.380s	395.394us	5	5	100.00
		otp_ctrl_csr_rw	1.970s	624.072us	20	20	100.00
		otp_ctrl_csr_aliasing	5.010s	132.990us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.620s	321.171us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.380s	395.394us	5	5	100.00
		otp_ctrl_csr_rw	1.970s	624.072us	20	20	100.00
		otp_ctrl_csr_aliasing	5.010s	132.990us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.620s	321.171us	20	20	100.00
V2		TOTAL			1100	1101	99.91
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.007m	19.009ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.007m	19.009ms	5	5	100.00
		otp_ctrl_tl_intg_err	30.910s	19.951ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.007m	19.009ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.007m	19.009ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	30.910s	19.951ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	17.000s	4.822ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	17.000s	4.822ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.007m	19.009ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.007m	19.009ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.007m	19.009ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.007m	19.009ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.007m	19.009ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.007m	19.009ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.007m	19.009ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.007m	19.009ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.007m	19.009ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.007m	19.009ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.007m	19.009ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.007m	19.009ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.007m	19.009ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.007m	19.009ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.007m	19.009ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	44.170s	13.857ms	200	200	100.00
		otp_ctrl_sec_cm	3.007m	19.009ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	44.170s	13.857ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	44.170s	13.857ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	44.170s	13.857ms	200	200	100.00
		otp_ctrl_macro_errs	1.167m	6.223ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	44.170s	13.857ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	44.170s	13.857ms	200	200	100.00
		otp_ctrl_sec_cm	3.007m	19.009ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	44.170s	13.857ms	200	200	100.00
		otp_ctrl_sec_cm	3.007m	19.009ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	44.170s	13.857ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	44.170s	13.857ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	44.170s	13.857ms	200	200	100.00
		otp_ctrl_macro_errs	1.167m	6.223ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	44.170s	13.857ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	44.170s	13.857ms	200	200	100.00
		otp_ctrl_sec_cm	3.007m	19.009ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.960s	2.381ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.236m	9.022ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	52.530s	15.458ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	52.530s	15.458ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	52.530s	15.458ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	52.530s	15.458ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	52.530s	15.458ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	17.000s	4.822ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	52.530s	15.458ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	17.000s	4.822ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.007m	19.009ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	15.720s	4.485ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	17.000s	4.822ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	17.000s	4.822ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.167m	6.223ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	14.660s	3.067ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.350h	1.062s	77	100	77.00
V3		TOTAL			78	101	77.23
		TOTAL			1318	1343	98.14

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.99	93.81	96.70	95.93	91.65	97.19	96.34	93.28

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 8 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 8 failures.
  - 35.otp_ctrl_stress_all_with_rand_reset.66720349212569171135713404073164295937255350918465638846171555583091181675652
    Line 15869, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 23661253849 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 23661253849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.otp_ctrl_stress_all_with_rand_reset.73496140818211269418961513552902674229375734687225910234294723610355644789824
    Line 946, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 150733734 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 150733734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 7 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 7 failures.
  - 2.otp_ctrl_stress_all_with_rand_reset.73153791907489966754804777876590048361067802859714911590630721477800864768131
    Line 125465, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1038817660117 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2390491623 [0x8e7c01e7] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 1038817660117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.otp_ctrl_stress_all_with_rand_reset.47419040781077319372425932938126565746275759209998886200670992160105821408324
    Line 57291, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 419853739886 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3021358954 [0xb416476a] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 419853739886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 0.otp_ctrl_stress_all_with_rand_reset.36371212442621667767508324961578508803265519460712977841159367536221811932570
    Line 34825, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26037669763 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 2523648969 [0x966bd3c9]) dai addr 708 rdata0 readout mismatch
  UVM_INFO @ 26037669763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 72.otp_ctrl_stress_all_with_rand_reset.33063341120446784481822856208717404883930153049265055834807433525138412568226
    Line 10896, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/72.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 21474479097 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 616 [0x268]) dai addr 268 rdata0 readout mismatch
  UVM_INFO @ 21474479097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(cio_test_en_o == *)' has 2 failures:
- Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 4.otp_ctrl_csr_mem_rw_with_rand_reset.44179460616259625536921850768097599014850178373792929140783895056915226263333
    Line 267, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  28952704 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  28952704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 95.otp_ctrl_stress_all_with_rand_reset.30332090643818447472863681109097774268465016500307690363128027170733802224158
    Line 14378, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/95.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 11526877827 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 11526877827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 58.otp_ctrl_stress_all_with_rand_reset.79038503198182081683142608314020087005855723295095157507616880602347780931238
    Line 653, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/58.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 133413478 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 133413478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 64.otp_ctrl_stress_all_with_rand_reset.93145604810828820289066049320665938541233534586127848886030868118302778420602
    Line 31796, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/64.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 28080009483 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 28080009483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 12.otp_ctrl_stress_all_with_rand_reset.93778384076566788422803062646684720110062839061199447114270300876212249831685
    Line 18960, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 187926741073 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 668 [0x29c]) dai addr 29c rdata0 readout mismatch
  UVM_INFO @ 187926741073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

25.otp_ctrl_stress_all_with_rand_reset.82753690478772950693415191275648276880514125470692154763852824404185831880017
Line 17489, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 11998929545 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 11999979545 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 12000154545 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 12001179545 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 12001179545 ps: (dv_base_reg.sv:325) [otp_ctrl_core_reg_block.direct_access_regwen] lock_lockable_flds          0 val

UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_check_error did not trigger max_delay:* has 1 failures:
- Test otp_ctrl_stress_all has 1 failures.
  - 35.otp_ctrl_stress_all.65745340553490745609884400084881104178176594531020090447932998522486321140965
    Line 3228, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 175078331 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_check_error did not trigger max_delay:5
  UVM_INFO @ 175078331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *d* rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 38.otp_ctrl_stress_all_with_rand_reset.59275131604000491680754903531272892564192793003554113125785665499042197987483
    Line 4167, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/38.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 96181039143 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 464 [0x1d0]) dai addr 1d0 rdata0 readout mismatch
  UVM_INFO @ 96181039143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```