OTP_CTRL Simulation Results

Sunday June 23 2024 23:02:35 UTC

GitHub Revision: 25e609d6bb

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 43520053114197278442322840927374150239284669988213580416404649115121474470865

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.740s	58.062us	1	1	100.00
V1	smoke	otp_ctrl_smoke	28.060s	4.247ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.920s	1.036ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.410s	584.892us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	8.740s	700.212us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.300s	315.691us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.520s	209.159us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.410s	584.892us	20	20	100.00
		otp_ctrl_csr_aliasing	6.300s	315.691us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.530s	564.119us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.600s	557.474us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	19.520s	1.232ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.270s	2.323ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	49.840s	29.951ms	10	10	100.00
		otp_ctrl_check_fail	1.027m	7.307ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	16.520s	4.680ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.784m	17.205ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.372m	28.964ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	36.520s	13.737ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	47.370s	19.659ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.089m	27.411ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.679m	14.825ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	59.090s	4.524ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	6.229m	49.787ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.130s	587.587us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.220s	202.410us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	9.340s	3.306ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	9.340s	3.306ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.920s	1.036ms	5	5	100.00
		otp_ctrl_csr_rw	2.410s	584.892us	20	20	100.00
		otp_ctrl_csr_aliasing	6.300s	315.691us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.010s	1.962ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.920s	1.036ms	5	5	100.00
		otp_ctrl_csr_rw	2.410s	584.892us	20	20	100.00
		otp_ctrl_csr_aliasing	6.300s	315.691us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.010s	1.962ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.341m	40.474ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.341m	40.474ms	5	5	100.00
		otp_ctrl_tl_intg_err	38.540s	18.891ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.341m	40.474ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.341m	40.474ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	38.540s	18.891ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	28.060s	4.247ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	28.060s	4.247ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.341m	40.474ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.341m	40.474ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.341m	40.474ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.341m	40.474ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.341m	40.474ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.341m	40.474ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.341m	40.474ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.341m	40.474ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.341m	40.474ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.341m	40.474ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.341m	40.474ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.341m	40.474ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.341m	40.474ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.341m	40.474ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.341m	40.474ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	47.370s	19.659ms	200	200	100.00
		otp_ctrl_sec_cm	3.341m	40.474ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	47.370s	19.659ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	47.370s	19.659ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	47.370s	19.659ms	200	200	100.00
		otp_ctrl_macro_errs	1.679m	14.825ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	47.370s	19.659ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	47.370s	19.659ms	200	200	100.00
		otp_ctrl_sec_cm	3.341m	40.474ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	47.370s	19.659ms	200	200	100.00
		otp_ctrl_sec_cm	3.341m	40.474ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	47.370s	19.659ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	47.370s	19.659ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	47.370s	19.659ms	200	200	100.00
		otp_ctrl_macro_errs	1.679m	14.825ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	47.370s	19.659ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	47.370s	19.659ms	200	200	100.00
		otp_ctrl_sec_cm	3.341m	40.474ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.270s	2.323ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.027m	7.307ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.784m	17.205ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.784m	17.205ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.784m	17.205ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.784m	17.205ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.784m	17.205ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	28.060s	4.247ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.784m	17.205ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	28.060s	4.247ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.341m	40.474ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	16.520s	4.680ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	28.060s	4.247ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	28.060s	4.247ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.679m	14.825ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.100s	7.003ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.199h	168.619ms	82	100	82.00
V3		TOTAL			83	101	82.18
		TOTAL			1325	1343	98.66

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.85	93.81	96.20	95.78	91.41	97.05	96.34	93.35

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 9 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 9 failures.

    • 10.otp_ctrl_stress_all_with_rand_reset.59730912353083388004043571886942619400215939503566536810857399283929607849463
      Line 57053, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 15089786374 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 15089786374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 13.otp_ctrl_stress_all_with_rand_reset.78655441180867710879459639623397883985058256529811242312970324165638652525814
      Line 11763, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 71325640598 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 71325640598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 7 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 7 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 7 failures.

    • 14.otp_ctrl_stress_all_with_rand_reset.14519752810962742937846963653197228134505573752049644691081826635895199314965
      Line 7268, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12842251240 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4191148017 [0xf9cfd7f1] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 12842251240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 42.otp_ctrl_stress_all_with_rand_reset.32373805158076954115649213705808797181200176230126716329568210013167170168344
      Line 10824, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 43985264799 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2043386000 [0x79cb9890] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 43985264799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• Offending '(cio_test_en_o == *)' has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 45.otp_ctrl_stress_all_with_rand_reset.64330139723912215246186892677512089172496377369010837790432471036287619005836
      Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 103320629 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 103320629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 75.otp_ctrl_stress_all_with_rand_reset.41928114463517394269164051588123523865826440451589750387817214234596725065965
      Line 35603, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/75.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 429402743277 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 429402743277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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