OTP_CTRL Simulation Results

Monday June 24 2024 23:02:35 UTC

GitHub Revision: `6e698b4dfe`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 102849012855470111388983783327793201144267754054590670930996118558901483180117

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.720s	59.158us	1	1	100.00
V1	smoke	otp_ctrl_smoke	19.060s	6.379ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.670s	189.877us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.320s	685.487us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	8.340s	3.382ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	3.770s	100.867us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.390s	1.677ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.320s	685.487us	20	20	100.00
		otp_ctrl_csr_aliasing	3.770s	100.867us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.590s	522.067us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.450s	39.143us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	20.020s	1.974ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.470s	1.889ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	31.010s	14.054ms	10	10	100.00
		otp_ctrl_check_fail	45.330s	23.893ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	11.940s	5.048ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.167m	30.566ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	47.360s	5.976ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	45.440s	14.607ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	43.530s	2.591ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.031m	21.467ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.638m	36.549ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	59.340s	21.389ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	8.160m	72.066ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.020s	556.393us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.770s	333.410us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	8.870s	472.562us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	8.870s	472.562us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.670s	189.877us	5	5	100.00
		otp_ctrl_csr_rw	2.320s	685.487us	20	20	100.00
		otp_ctrl_csr_aliasing	3.770s	100.867us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.840s	1.848ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.670s	189.877us	5	5	100.00
		otp_ctrl_csr_rw	2.320s	685.487us	20	20	100.00
		otp_ctrl_csr_aliasing	3.770s	100.867us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.840s	1.848ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.788m	154.745ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.788m	154.745ms	5	5	100.00
		otp_ctrl_tl_intg_err	22.330s	3.423ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.788m	154.745ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.788m	154.745ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	22.330s	3.423ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	19.060s	6.379ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	19.060s	6.379ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.788m	154.745ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.788m	154.745ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.788m	154.745ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.788m	154.745ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.788m	154.745ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.788m	154.745ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.788m	154.745ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.788m	154.745ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.788m	154.745ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.788m	154.745ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.788m	154.745ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.788m	154.745ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.788m	154.745ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.788m	154.745ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.788m	154.745ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.530s	2.591ms	200	200	100.00
		otp_ctrl_sec_cm	3.788m	154.745ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.530s	2.591ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.530s	2.591ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.530s	2.591ms	200	200	100.00
		otp_ctrl_macro_errs	1.638m	36.549ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.530s	2.591ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.530s	2.591ms	200	200	100.00
		otp_ctrl_sec_cm	3.788m	154.745ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.530s	2.591ms	200	200	100.00
		otp_ctrl_sec_cm	3.788m	154.745ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.530s	2.591ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.530s	2.591ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.530s	2.591ms	200	200	100.00
		otp_ctrl_macro_errs	1.638m	36.549ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.530s	2.591ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.530s	2.591ms	200	200	100.00
		otp_ctrl_sec_cm	3.788m	154.745ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.470s	1.889ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	45.330s	23.893ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.167m	30.566ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.167m	30.566ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.167m	30.566ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.167m	30.566ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.167m	30.566ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	19.060s	6.379ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.167m	30.566ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	19.060s	6.379ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.788m	154.745ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	11.940s	5.048ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	19.060s	6.379ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	19.060s	6.379ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.638m	36.549ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.110s	7.588ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	54.689m	508.551ms	84	100	84.00
V3		TOTAL			85	101	84.16
		TOTAL			1327	1343	98.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.89	93.76	96.20	95.75	91.89	97.00	96.34	93.28

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 9 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 9 failures.
  - 13.otp_ctrl_stress_all_with_rand_reset.53033055411577726036637918881219012209260859964159510461145255879981886749940
    Line 3192, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 30993269759 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 30993269759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.otp_ctrl_stress_all_with_rand_reset.10464484309986472945094192084327290784720581645213391430483159156413640185547
    Line 2544, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6184240352 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 6184240352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 4 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 4 failures.
  - 55.otp_ctrl_stress_all_with_rand_reset.109997528951142570365512367899252606482313873306554715147448948690725715457166
    Line 48281, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/55.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 81712868435 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (470923915 [0x1c11ba8b] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 81712868435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 56.otp_ctrl_stress_all_with_rand_reset.109996668716223622786407179254872892866760178445843943192343666715024252145992
    Line 14458, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/56.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4381365834 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1672622551 [0x63b231d7] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 4381365834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 2 failures:

Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

27.otp_ctrl_stress_all_with_rand_reset.81339819605067191621653657534342783605999393891595990795948734802511542298899
Line 87232, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 98953676514 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 98954043858 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 98954105082 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 98954737730 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 98954860178 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

38.otp_ctrl_stress_all_with_rand_reset.26772308781187315126676052519992592730903969566526604759209550125489371677352
Line 5356, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/38.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 27447891556 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 27448683229 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 27448724896 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 27449599903 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 27449641570 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

Offending '(cio_test_en_o == *)' has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 18.otp_ctrl_stress_all_with_rand_reset.67198622378552374285292083450971527612302003648695311588716861591766780495666
    Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  29367732 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  29367732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```