OTP_CTRL Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: `3fd3528c8c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.680s	53.665us	1	1	100.00
V1	smoke	otp_ctrl_smoke	26.010s	7.778ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.580s	97.149us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.190s	585.066us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	15.030s	6.866ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.390s	212.591us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.970s	1.525ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.190s	585.066us	20	20	100.00
		otp_ctrl_csr_aliasing	6.390s	212.591us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.810s	540.751us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.440s	65.689us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	18.850s	618.324us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.140s	2.824ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	1.026m	32.086ms	10	10	100.00
		otp_ctrl_check_fail	1.289m	8.930ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	17.790s	5.169ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	34.780s	2.706ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	57.040s	24.060ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	31.720s	11.499ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	39.540s	2.480ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	54.500s	15.719ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.025m	11.230ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	51.470s	31.949ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	14.469m	76.085ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.370s	582.531us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.240s	958.682us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	10.530s	2.589ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	10.530s	2.589ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.580s	97.149us	5	5	100.00
		otp_ctrl_csr_rw	2.190s	585.066us	20	20	100.00
		otp_ctrl_csr_aliasing	6.390s	212.591us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.620s	1.899ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.580s	97.149us	5	5	100.00
		otp_ctrl_csr_rw	2.190s	585.066us	20	20	100.00
		otp_ctrl_csr_aliasing	6.390s	212.591us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.620s	1.899ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	5.409m	154.673ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	5.409m	154.673ms	5	5	100.00
		otp_ctrl_tl_intg_err	23.530s	2.021ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	5.409m	154.673ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	5.409m	154.673ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	23.530s	2.021ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	26.010s	7.778ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	26.010s	7.778ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	5.409m	154.673ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	5.409m	154.673ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	5.409m	154.673ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	5.409m	154.673ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	5.409m	154.673ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	5.409m	154.673ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	5.409m	154.673ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	5.409m	154.673ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	5.409m	154.673ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	5.409m	154.673ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	5.409m	154.673ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	5.409m	154.673ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	5.409m	154.673ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	5.409m	154.673ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	5.409m	154.673ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.540s	2.480ms	200	200	100.00
		otp_ctrl_sec_cm	5.409m	154.673ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.540s	2.480ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.540s	2.480ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.540s	2.480ms	200	200	100.00
		otp_ctrl_macro_errs	1.025m	11.230ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.540s	2.480ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.540s	2.480ms	200	200	100.00
		otp_ctrl_sec_cm	5.409m	154.673ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.540s	2.480ms	200	200	100.00
		otp_ctrl_sec_cm	5.409m	154.673ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.540s	2.480ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.540s	2.480ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.540s	2.480ms	200	200	100.00
		otp_ctrl_macro_errs	1.025m	11.230ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.540s	2.480ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.540s	2.480ms	200	200	100.00
		otp_ctrl_sec_cm	5.409m	154.673ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.140s	2.824ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.289m	8.930ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	34.780s	2.706ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	34.780s	2.706ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	34.780s	2.706ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	34.780s	2.706ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	34.780s	2.706ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	26.010s	7.778ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	34.780s	2.706ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	26.010s	7.778ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	5.409m	154.673ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	17.790s	5.169ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	26.010s	7.778ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	26.010s	7.778ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.025m	11.230ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.930s	5.944ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.093h	1.062s	89	100	89.00
V3		TOTAL			90	101	89.11
		TOTAL			1332	1343	99.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.82	93.81	96.18	95.85	91.17	97.05	96.34	93.35

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 5 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 5 failures.
  - 1.otp_ctrl_stress_all_with_rand_reset.115122334001728827197583181697022138243887201657215009103178852711286656386564
    Line 49718, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 202064971183 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 202064971183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.otp_ctrl_stress_all_with_rand_reset.35063948382289363517793854287287720407490366471148162494855917895038321809453
    Line 9080, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 32160618531 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 32160618531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 3 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 3 failures.
  - 3.otp_ctrl_stress_all_with_rand_reset.47218901697676909788488131972179621936314153567755861140506957820057521280782
    Line 36934, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 661133609609 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (324252696 [0x1353b418] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 661133609609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.otp_ctrl_stress_all_with_rand_reset.7215393946511714656514205755187078864265409574155085324578318383986620314732
    Line 35246, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 146737358506 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2693896369 [0xa09198b1] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 146737358506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 2 failures:

Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

71.otp_ctrl_stress_all_with_rand_reset.54956737780404749723747721480006956638095775039369538546837767625447907371431
Line 18518, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/71.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 124850016691 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 124850593621 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 124850824393 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 124851670557 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 124852055177 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

98.otp_ctrl_stress_all_with_rand_reset.51469055859875368842321038314060761964414946511304041683105223413358868995073
Line 2773, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/98.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 697816002 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 698545157 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 698565990 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 699399310 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 699482642 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 60.otp_ctrl_stress_all_with_rand_reset.99627766098222068973867886730035025048566219538153382766689901464901471600912
    Line 41669, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/60.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18539415086 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 18539415086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```