OTP_CTRL Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: be1c4a4f52

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.670s	55.370us	1	1	100.00
V1	smoke	otp_ctrl_smoke	16.750s	1.051ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.410s	107.081us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.370s	662.648us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	12.470s	6.785ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.660s	202.521us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	3.620s	109.487us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.370s	662.648us	20	20	100.00
		otp_ctrl_csr_aliasing	6.660s	202.521us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.430s	72.083us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.460s	135.162us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	17.900s	1.194ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	9.370s	3.009ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	31.880s	2.990ms	10	10	100.00
		otp_ctrl_check_fail	1.360m	8.881ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	12.950s	3.536ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	43.220s	7.782ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	55.570s	7.544ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	45.770s	13.581ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	42.960s	13.502ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	50.720s	17.394ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.658m	12.561ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.131m	20.290ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	5.779m	41.156ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.030s	592.117us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.670s	1.116ms	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	9.340s	2.758ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	9.340s	2.758ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.410s	107.081us	5	5	100.00
		otp_ctrl_csr_rw	2.370s	662.648us	20	20	100.00
		otp_ctrl_csr_aliasing	6.660s	202.521us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.530s	154.946us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.410s	107.081us	5	5	100.00
		otp_ctrl_csr_rw	2.370s	662.648us	20	20	100.00
		otp_ctrl_csr_aliasing	6.660s	202.521us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.530s	154.946us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.609m	24.191ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.609m	24.191ms	5	5	100.00
		otp_ctrl_tl_intg_err	28.400s	21.890ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.609m	24.191ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.609m	24.191ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	28.400s	21.890ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	16.750s	1.051ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	16.750s	1.051ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.609m	24.191ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.609m	24.191ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.609m	24.191ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.609m	24.191ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.609m	24.191ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.609m	24.191ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.609m	24.191ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.609m	24.191ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.609m	24.191ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.609m	24.191ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.609m	24.191ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.609m	24.191ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.609m	24.191ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.609m	24.191ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.609m	24.191ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.960s	13.502ms	200	200	100.00
		otp_ctrl_sec_cm	3.609m	24.191ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.960s	13.502ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.960s	13.502ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.960s	13.502ms	200	200	100.00
		otp_ctrl_macro_errs	1.658m	12.561ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.960s	13.502ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.960s	13.502ms	200	200	100.00
		otp_ctrl_sec_cm	3.609m	24.191ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.960s	13.502ms	200	200	100.00
		otp_ctrl_sec_cm	3.609m	24.191ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.960s	13.502ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.960s	13.502ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.960s	13.502ms	200	200	100.00
		otp_ctrl_macro_errs	1.658m	12.561ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.960s	13.502ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.960s	13.502ms	200	200	100.00
		otp_ctrl_sec_cm	3.609m	24.191ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	9.370s	3.009ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.360m	8.881ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	43.220s	7.782ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	43.220s	7.782ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	43.220s	7.782ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	43.220s	7.782ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	43.220s	7.782ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	16.750s	1.051ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	43.220s	7.782ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	16.750s	1.051ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.609m	24.191ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	12.950s	3.536ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	16.750s	1.051ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	16.750s	1.051ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.658m	12.561ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	23.020s	7.014ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.497h	2.968s	85	100	85.00
V3		TOTAL			86	101	85.15
		TOTAL			1328	1343	98.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.00	93.76	96.65	96.21	91.65	97.15	96.34	93.21

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 7 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 7 failures.

    • 4.otp_ctrl_stress_all_with_rand_reset.5063124099492642192901927143924118897028567049638988784515184750525967252800
      Line 57961, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 38524425536 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 38524425536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.otp_ctrl_stress_all_with_rand_reset.81669991176840433250008544626135780432076911058231875071549110735142466182580
      Line 67693, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 320752187597 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 320752187597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 6 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 6 failures.

    • 23.otp_ctrl_stress_all_with_rand_reset.8015585994463287429434774611273242330788778597550641099003985019908371779714
      Line 13165, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 757510945 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3143713642 [0xbb61436a] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 757510945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 26.otp_ctrl_stress_all_with_rand_reset.99074942213388325962360821688284294293437162503754080205154760367128014764023
      Line 92941, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 52713495895 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1372013514 [0x51c743ca] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 52713495895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 4 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 30.otp_ctrl_stress_all_with_rand_reset.66667253538899059815624246281574001917792092047022753759958742516930277946638
      Line 36110, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 16485026708 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 16485026708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(cio_test_en_o == *)' has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 91.otp_ctrl_stress_all_with_rand_reset.76131439916029361706888264514038925028702162822893888104979845417028486903493
      Line 121942, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/91.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 99805525800 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 99805525800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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