8db2a18db1| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | wake_up | otp_ctrl_wake_up | 1.930s | 799.243us | 1 | 1 | 100.00 |
| V1 | smoke | otp_ctrl_smoke | 18.980s | 8.113ms | 45 | 50 | 90.00 |
| V1 | csr_hw_reset | otp_ctrl_csr_hw_reset | 4.750s | 1.608ms | 5 | 5 | 100.00 |
| V1 | csr_rw | otp_ctrl_csr_rw | 1.840s | 173.528us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otp_ctrl_csr_bit_bash | 16.730s | 6.802ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otp_ctrl_csr_aliasing | 6.060s | 1.193ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otp_ctrl_csr_mem_rw_with_rand_reset | 4.040s | 112.267us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otp_ctrl_csr_rw | 1.840s | 173.528us | 20 | 20 | 100.00 |
| otp_ctrl_csr_aliasing | 6.060s | 1.193ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otp_ctrl_mem_walk | 1.400s | 131.048us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otp_ctrl_mem_partial_access | 1.590s | 560.196us | 5 | 5 | 100.00 |
| V1 | TOTAL | 111 | 116 | 95.69 | |||
| V2 | dai_access_partition_walk | otp_ctrl_partition_walk | 17.650s | 576.326us | 1 | 1 | 100.00 |
| V2 | init_fail | otp_ctrl_init_fail | 8.030s | 2.478ms | 279 | 300 | 93.00 |
| V2 | partition_check | otp_ctrl_background_chks | 56.470s | 23.003ms | 10 | 10 | 100.00 |
| otp_ctrl_check_fail | 58.110s | 15.321ms | 40 | 50 | 80.00 | ||
| V2 | regwen_during_otp_init | otp_ctrl_regwen | 14.370s | 4.351ms | 44 | 50 | 88.00 |
| V2 | partition_lock | otp_ctrl_dai_lock | 38.410s | 3.197ms | 43 | 50 | 86.00 |
| V2 | interface_key_check | otp_ctrl_parallel_key_req | 37.350s | 1.672ms | 40 | 50 | 80.00 |
| V2 | lc_interactions | otp_ctrl_parallel_lc_req | 31.270s | 10.448ms | 41 | 50 | 82.00 |
| otp_ctrl_parallel_lc_esc | 40.020s | 12.639ms | 180 | 200 | 90.00 | ||
| V2 | otp_dai_errors | otp_ctrl_dai_errs | 39.150s | 5.942ms | 42 | 50 | 84.00 |
| V2 | otp_macro_errors | otp_ctrl_macro_errs | 42.180s | 1.940ms | 44 | 50 | 88.00 |
| V2 | test_access | otp_ctrl_test_access | 2.668m | 21.061ms | 42 | 50 | 84.00 |
| V2 | stress_all | otp_ctrl_stress_all | 8.028m | 184.125ms | 45 | 50 | 90.00 |
| V2 | intr_test | otp_ctrl_intr_test | 1.880s | 519.612us | 50 | 50 | 100.00 |
| V2 | alert_test | otp_ctrl_alert_test | 3.380s | 914.139us | 47 | 50 | 94.00 |
| V2 | tl_d_oob_addr_access | otp_ctrl_tl_errors | 6.270s | 747.909us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otp_ctrl_tl_errors | 6.270s | 747.909us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otp_ctrl_csr_hw_reset | 4.750s | 1.608ms | 5 | 5 | 100.00 |
| otp_ctrl_csr_rw | 1.840s | 173.528us | 20 | 20 | 100.00 | ||
| otp_ctrl_csr_aliasing | 6.060s | 1.193ms | 5 | 5 | 100.00 | ||
| otp_ctrl_same_csr_outstanding | 5.890s | 1.844ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otp_ctrl_csr_hw_reset | 4.750s | 1.608ms | 5 | 5 | 100.00 |
| otp_ctrl_csr_rw | 1.840s | 173.528us | 20 | 20 | 100.00 | ||
| otp_ctrl_csr_aliasing | 6.060s | 1.193ms | 5 | 5 | 100.00 | ||
| otp_ctrl_same_csr_outstanding | 5.890s | 1.844ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 988 | 1101 | 89.74 | |||
| V2S | sec_cm_additional_check | otp_ctrl_sec_cm | 4.925m | 169.713ms | 5 | 5 | 100.00 |
| V2S | tl_intg_err | otp_ctrl_sec_cm | 4.925m | 169.713ms | 5 | 5 | 100.00 |
| otp_ctrl_tl_intg_err | 20.630s | 4.714ms | 20 | 20 | 100.00 | ||
| V2S | prim_count_check | otp_ctrl_sec_cm | 4.925m | 169.713ms | 5 | 5 | 100.00 |
| V2S | prim_fsm_check | otp_ctrl_sec_cm | 4.925m | 169.713ms | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | otp_ctrl_tl_intg_err | 20.630s | 4.714ms | 20 | 20 | 100.00 |
| V2S | sec_cm_secret_mem_scramble | otp_ctrl_smoke | 18.980s | 8.113ms | 45 | 50 | 90.00 |
| V2S | sec_cm_part_mem_digest | otp_ctrl_smoke | 18.980s | 8.113ms | 45 | 50 | 90.00 |
| V2S | sec_cm_dai_fsm_sparse | otp_ctrl_sec_cm | 4.925m | 169.713ms | 5 | 5 | 100.00 |
| V2S | sec_cm_kdi_fsm_sparse | otp_ctrl_sec_cm | 4.925m | 169.713ms | 5 | 5 | 100.00 |
| V2S | sec_cm_lci_fsm_sparse | otp_ctrl_sec_cm | 4.925m | 169.713ms | 5 | 5 | 100.00 |
| V2S | sec_cm_part_fsm_sparse | otp_ctrl_sec_cm | 4.925m | 169.713ms | 5 | 5 | 100.00 |
| V2S | sec_cm_scrmbl_fsm_sparse | otp_ctrl_sec_cm | 4.925m | 169.713ms | 5 | 5 | 100.00 |
| V2S | sec_cm_timer_fsm_sparse | otp_ctrl_sec_cm | 4.925m | 169.713ms | 5 | 5 | 100.00 |
| V2S | sec_cm_dai_ctr_redun | otp_ctrl_sec_cm | 4.925m | 169.713ms | 5 | 5 | 100.00 |
| V2S | sec_cm_kdi_seed_ctr_redun | otp_ctrl_sec_cm | 4.925m | 169.713ms | 5 | 5 | 100.00 |
| V2S | sec_cm_kdi_entropy_ctr_redun | otp_ctrl_sec_cm | 4.925m | 169.713ms | 5 | 5 | 100.00 |
| V2S | sec_cm_lci_ctr_redun | otp_ctrl_sec_cm | 4.925m | 169.713ms | 5 | 5 | 100.00 |
| V2S | sec_cm_part_ctr_redun | otp_ctrl_sec_cm | 4.925m | 169.713ms | 5 | 5 | 100.00 |
| V2S | sec_cm_scrmbl_ctr_redun | otp_ctrl_sec_cm | 4.925m | 169.713ms | 5 | 5 | 100.00 |
| V2S | sec_cm_timer_integ_ctr_redun | otp_ctrl_sec_cm | 4.925m | 169.713ms | 5 | 5 | 100.00 |
| V2S | sec_cm_timer_cnsty_ctr_redun | otp_ctrl_sec_cm | 4.925m | 169.713ms | 5 | 5 | 100.00 |
| V2S | sec_cm_timer_lfsr_redun | otp_ctrl_sec_cm | 4.925m | 169.713ms | 5 | 5 | 100.00 |
| V2S | sec_cm_dai_fsm_local_esc | otp_ctrl_parallel_lc_esc | 40.020s | 12.639ms | 180 | 200 | 90.00 |
| otp_ctrl_sec_cm | 4.925m | 169.713ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_lci_fsm_local_esc | otp_ctrl_parallel_lc_esc | 40.020s | 12.639ms | 180 | 200 | 90.00 |
| V2S | sec_cm_kdi_fsm_local_esc | otp_ctrl_parallel_lc_esc | 40.020s | 12.639ms | 180 | 200 | 90.00 |
| V2S | sec_cm_part_fsm_local_esc | otp_ctrl_parallel_lc_esc | 40.020s | 12.639ms | 180 | 200 | 90.00 |
| otp_ctrl_macro_errs | 42.180s | 1.940ms | 44 | 50 | 88.00 | ||
| V2S | sec_cm_scrmbl_fsm_local_esc | otp_ctrl_parallel_lc_esc | 40.020s | 12.639ms | 180 | 200 | 90.00 |
| V2S | sec_cm_timer_fsm_local_esc | otp_ctrl_parallel_lc_esc | 40.020s | 12.639ms | 180 | 200 | 90.00 |
| otp_ctrl_sec_cm | 4.925m | 169.713ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_dai_fsm_global_esc | otp_ctrl_parallel_lc_esc | 40.020s | 12.639ms | 180 | 200 | 90.00 |
| otp_ctrl_sec_cm | 4.925m | 169.713ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_lci_fsm_global_esc | otp_ctrl_parallel_lc_esc | 40.020s | 12.639ms | 180 | 200 | 90.00 |
| V2S | sec_cm_kdi_fsm_global_esc | otp_ctrl_parallel_lc_esc | 40.020s | 12.639ms | 180 | 200 | 90.00 |
| V2S | sec_cm_part_fsm_global_esc | otp_ctrl_parallel_lc_esc | 40.020s | 12.639ms | 180 | 200 | 90.00 |
| otp_ctrl_macro_errs | 42.180s | 1.940ms | 44 | 50 | 88.00 | ||
| V2S | sec_cm_scrmbl_fsm_global_esc | otp_ctrl_parallel_lc_esc | 40.020s | 12.639ms | 180 | 200 | 90.00 |
| V2S | sec_cm_timer_fsm_global_esc | otp_ctrl_parallel_lc_esc | 40.020s | 12.639ms | 180 | 200 | 90.00 |
| otp_ctrl_sec_cm | 4.925m | 169.713ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_part_data_reg_integrity | otp_ctrl_init_fail | 8.030s | 2.478ms | 279 | 300 | 93.00 |
| V2S | sec_cm_part_data_reg_bkgn_chk | otp_ctrl_check_fail | 58.110s | 15.321ms | 40 | 50 | 80.00 |
| V2S | sec_cm_part_mem_regren | otp_ctrl_dai_lock | 38.410s | 3.197ms | 43 | 50 | 86.00 |
| V2S | sec_cm_part_mem_sw_unreadable | otp_ctrl_dai_lock | 38.410s | 3.197ms | 43 | 50 | 86.00 |
| V2S | sec_cm_part_mem_sw_unwritable | otp_ctrl_dai_lock | 38.410s | 3.197ms | 43 | 50 | 86.00 |
| V2S | sec_cm_lc_part_mem_sw_noaccess | otp_ctrl_dai_lock | 38.410s | 3.197ms | 43 | 50 | 86.00 |
| V2S | sec_cm_access_ctrl_mubi | otp_ctrl_dai_lock | 38.410s | 3.197ms | 43 | 50 | 86.00 |
| V2S | sec_cm_token_valid_ctrl_mubi | otp_ctrl_smoke | 18.980s | 8.113ms | 45 | 50 | 90.00 |
| V2S | sec_cm_lc_ctrl_intersig_mubi | otp_ctrl_dai_lock | 38.410s | 3.197ms | 43 | 50 | 86.00 |
| V2S | sec_cm_test_bus_lc_gated | otp_ctrl_smoke | 18.980s | 8.113ms | 45 | 50 | 90.00 |
| V2S | sec_cm_test_tl_lc_gate_fsm_sparse | otp_ctrl_sec_cm | 4.925m | 169.713ms | 5 | 5 | 100.00 |
| V2S | sec_cm_direct_access_config_regwen | otp_ctrl_regwen | 14.370s | 4.351ms | 44 | 50 | 88.00 |
| V2S | sec_cm_check_trigger_config_regwen | otp_ctrl_smoke | 18.980s | 8.113ms | 45 | 50 | 90.00 |
| V2S | sec_cm_check_config_regwen | otp_ctrl_smoke | 18.980s | 8.113ms | 45 | 50 | 90.00 |
| V2S | sec_cm_macro_mem_integrity | otp_ctrl_macro_errs | 42.180s | 1.940ms | 44 | 50 | 88.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | otp_ctrl_low_freq_read | otp_ctrl_low_freq_read | 11.070s | 3.016ms | 1 | 1 | 100.00 |
| V3 | stress_all_with_rand_reset | otp_ctrl_stress_all_with_rand_reset | 1.383h | 1.600s | 69 | 100 | 69.00 |
| V3 | TOTAL | 70 | 101 | 69.31 | |||
| TOTAL | 1194 | 1343 | 88.91 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 8 | 88.89 |
| V2 | 17 | 17 | 5 | 29.41 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 2 | 1 | 50.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 94.79 | 93.71 | 96.65 | 95.99 | 90.69 | 97.05 | 96.28 | 93.14 |
Exit reason: Error: User command failed Job returned non-zero exit code has 101 failures:
1.otp_ctrl_init_fail.1993627456949065922975707251525759059841134705451893759868910463032565401154
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_init_fail/latest/run.log
[make]: simulate
cd /workspace/1.otp_ctrl_init_fail/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362776130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.362776130
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jun 27 19:18 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 255
26.otp_ctrl_init_fail.106916609297153475025899939074732874061647626855456422281442708441173792746643
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/26.otp_ctrl_init_fail/latest/run.log
[make]: simulate
cd /workspace/26.otp_ctrl_init_fail/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114991763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.1114991763
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jun 27 19:19 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 255
... and 16 more failures.
2.otp_ctrl_stress_all.100964568076469770352859260473390140495183121363655540948479090972413286988604
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all/latest/run.log
[make]: simulate
cd /workspace/2.otp_ctrl_stress_all/latest && /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451984188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.451984188
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jun 27 19:16 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 255
4.otp_ctrl_stress_all.61267212210055687989289802986303674460007123672596686545209601430746873700672
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all/latest/run.log
[make]: simulate
cd /workspace/4.otp_ctrl_stress_all/latest && /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296460608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.296460608
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jun 27 19:17 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 255
... and 2 more failures.
4.otp_ctrl_parallel_key_req.16143561816308089496204757420262478061442420598635344862694339626151525044907
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_key_req/latest/run.log
[make]: simulate
cd /workspace/4.otp_ctrl_parallel_key_req/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770527915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.770527915
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jun 27 19:17 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 255
17.otp_ctrl_parallel_key_req.10051689195486708339529289761208617327698845915410993295861911994619104805308
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_key_req/latest/run.log
[make]: simulate
cd /workspace/17.otp_ctrl_parallel_key_req/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206417340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.2206417340
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jun 27 19:18 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 255
... and 6 more failures.
5.otp_ctrl_dai_errs.103223512882714241770485909356800065914968570006244926043848241633802573610663
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_dai_errs/latest/run.log
[make]: simulate
cd /workspace/5.otp_ctrl_dai_errs/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789244583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.2789244583
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jun 27 19:17 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 255
8.otp_ctrl_dai_errs.92598427550681333773168132718568095181007085600211122061565458815995670076507
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_dai_errs/latest/run.log
[make]: simulate
cd /workspace/8.otp_ctrl_dai_errs/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84057179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.84057179
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jun 27 19:17 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 255
... and 4 more failures.
5.otp_ctrl_stress_all_with_rand_reset.77192014888967824800110987680013907655056109914495806805799373682404361637360
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/5.otp_ctrl_stress_all_with_rand_reset/latest && /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923143664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all_with_rand_reset.923143664
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jun 27 19:17 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 255
7.otp_ctrl_stress_all_with_rand_reset.24301269410284152035353812650112138518121162410337882427861679980634147257918
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/7.otp_ctrl_stress_all_with_rand_reset/latest && /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729573950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all_with_rand_reset.2729573950
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jun 27 19:17 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 255
... and 8 more failures.
Job otp_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 31 failures:
Test otp_ctrl_check_fail has 4 failures.
15.otp_ctrl_check_fail.50154831847774123837141657459696875734175489588465154680354639095060874986863
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_check_fail/latest/run.log
Job ID: smart:04d91b33-5a47-4865-a3c0-c5ee6d157450
42.otp_ctrl_check_fail.108977497672720959622153912507846758428126528960979084151040941368784369416168
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/42.otp_ctrl_check_fail/latest/run.log
Job ID: smart:fd499326-aff7-46d3-8db0-5fe009ea75c3
... and 2 more failures.
Test otp_ctrl_stress_all_with_rand_reset has 4 failures.
15.otp_ctrl_stress_all_with_rand_reset.80705913539824182030691904196136014158003291015591791893344636299317858241779
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:2d94827b-f04a-4eeb-8978-db238112e70b
45.otp_ctrl_stress_all_with_rand_reset.7738827314597400256835308459017029977116611509812790733355859203791637636351
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:8322279a-1f11-421e-a600-65f2a0c6ea56
... and 2 more failures.
Test otp_ctrl_alert_test has 1 failures.
15.otp_ctrl_alert_test.48707629553160890349295646125217733833802808862471066212993052140517829395285
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_alert_test/latest/run.log
Job ID: smart:cf9e8600-3246-4a09-9f18-03e5aac5aaec
Test otp_ctrl_parallel_lc_req has 3 failures.
16.otp_ctrl_parallel_lc_req.16596538702617176524226982709485545671691267219242572347797332139139967045146
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_req/latest/run.log
Job ID: smart:c50f1bfb-bcf0-48b2-b664-0e6bfecd3f40
21.otp_ctrl_parallel_lc_req.114129679018758746552693223327251632263836081068276124829255675762134524942234
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_req/latest/run.log
Job ID: smart:79e01383-d7bf-4e99-b9c2-d28d94ea1d4f
... and 1 more failures.
Test otp_ctrl_parallel_lc_esc has 4 failures.
16.otp_ctrl_parallel_lc_esc.80616449293684572820974050901046390264953339419956759989208423836668517187860
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_esc/latest/run.log
Job ID: smart:fff27e6a-a298-4c72-98c4-c4e60229fbab
47.otp_ctrl_parallel_lc_esc.59398985030517549176976733784673256535289571852299747196508786877940854735702
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_esc/latest/run.log
Job ID: smart:cc12335c-fab3-496e-b66c-c95f56c64e52
... and 2 more failures.
... and 9 more tests.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 8 failures:
12.otp_ctrl_stress_all_with_rand_reset.70962508983815750349867405158265251689854652340250821322021780871463466641572
Line 330, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 35175184 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (154700161 [0x9388981] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 35175184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.otp_ctrl_stress_all_with_rand_reset.49915795660946729930886288399768610576557159068864898081029121862303346555435
Line 489, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11299096032 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1244640589 [0x4a2fb54d] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 11299096032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 7 failures:
13.otp_ctrl_stress_all_with_rand_reset.1403946217545368063572204012476578313884785622071744702677200486806530289837
Line 61340, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 195238959028 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 195238959028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.otp_ctrl_stress_all_with_rand_reset.9509612018520863206316261773582467248761992786157355016577688717176513143885
Line 111591, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 52896325484 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 52896325484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Offending '(cio_test_en_o == *)' has 2 failures:
26.otp_ctrl_stress_all_with_rand_reset.115705305929351629856350196134113189660493743613848322201783154760560349182530
Line 40420, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all_with_rand_reset/latest/run.log
Offending '(cio_test_en_o == 0)'
UVM_ERROR @ 93035359796 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 93035359796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
80.otp_ctrl_stress_all_with_rand_reset.56382520904469240569194854300683503748633848011769771024341054683128399539179
Line 7833, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/80.otp_ctrl_stress_all_with_rand_reset/latest/run.log
Offending '(cio_test_en_o == 0)'
UVM_ERROR @ 1063800992 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 1063800992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---