OTP_CTRL Simulation Results

Friday June 28 2024 23:02:02 UTC

GitHub Revision: `3d5220a43f`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 73442097946972310753089853920865571566707682704390544987111276126114608747389

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.790s	101.061us	1	1	100.00
V1	smoke	otp_ctrl_smoke	19.500s	2.317ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.780s	396.992us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.000s	630.366us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	11.290s	6.878ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	7.660s	3.096ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.460s	419.340us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.000s	630.366us	20	20	100.00
		otp_ctrl_csr_aliasing	7.660s	3.096ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.450s	73.990us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.480s	505.720us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	18.360s	627.530us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.300s	2.530ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	35.350s	1.619ms	10	10	100.00
		otp_ctrl_check_fail	1.633m	32.067ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	16.130s	4.121ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	57.770s	22.750ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	49.380s	16.504ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	38.210s	13.197ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	36.220s	2.258ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	54.620s	18.014ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	49.060s	19.540ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	58.720s	25.048ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	5.565m	39.286ms	49	50	98.00
V2	intr_test	otp_ctrl_intr_test	2.050s	587.586us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.290s	319.574us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.210s	166.515us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.210s	166.515us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.780s	396.992us	5	5	100.00
		otp_ctrl_csr_rw	2.000s	630.366us	20	20	100.00
		otp_ctrl_csr_aliasing	7.660s	3.096ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	6.380s	1.936ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.780s	396.992us	5	5	100.00
		otp_ctrl_csr_rw	2.000s	630.366us	20	20	100.00
		otp_ctrl_csr_aliasing	7.660s	3.096ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	6.380s	1.936ms	20	20	100.00
V2		TOTAL			1100	1101	99.91
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	6.185m	154.747ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	6.185m	154.747ms	5	5	100.00
		otp_ctrl_tl_intg_err	22.620s	2.066ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	6.185m	154.747ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	6.185m	154.747ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	22.620s	2.066ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	19.500s	2.317ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	19.500s	2.317ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	6.185m	154.747ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	6.185m	154.747ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	6.185m	154.747ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	6.185m	154.747ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	6.185m	154.747ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	6.185m	154.747ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	6.185m	154.747ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	6.185m	154.747ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	6.185m	154.747ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	6.185m	154.747ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	6.185m	154.747ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	6.185m	154.747ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	6.185m	154.747ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	6.185m	154.747ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	6.185m	154.747ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.220s	2.258ms	200	200	100.00
		otp_ctrl_sec_cm	6.185m	154.747ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.220s	2.258ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.220s	2.258ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.220s	2.258ms	200	200	100.00
		otp_ctrl_macro_errs	49.060s	19.540ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.220s	2.258ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.220s	2.258ms	200	200	100.00
		otp_ctrl_sec_cm	6.185m	154.747ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.220s	2.258ms	200	200	100.00
		otp_ctrl_sec_cm	6.185m	154.747ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.220s	2.258ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.220s	2.258ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.220s	2.258ms	200	200	100.00
		otp_ctrl_macro_errs	49.060s	19.540ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.220s	2.258ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.220s	2.258ms	200	200	100.00
		otp_ctrl_sec_cm	6.185m	154.747ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.300s	2.530ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.633m	32.067ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	57.770s	22.750ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	57.770s	22.750ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	57.770s	22.750ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	57.770s	22.750ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	57.770s	22.750ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	19.500s	2.317ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	57.770s	22.750ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	19.500s	2.317ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	6.185m	154.747ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	16.130s	4.121ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	19.500s	2.317ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	19.500s	2.317ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	49.060s	19.540ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	14.010s	3.045ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	59.636m	1.870s	78	100	78.00
V3		TOTAL			79	101	78.22
		TOTAL			1320	1343	98.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.93	93.81	96.30	95.91	91.65	97.05	96.34	93.42

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 9 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 9 failures.
  - 3.otp_ctrl_stress_all_with_rand_reset.102330800039376262039396516157659067961246272147652122625876806537444975490654
    Line 9746, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 45972089298 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 45972089298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.otp_ctrl_stress_all_with_rand_reset.86247691215955550938907037913857285114450987522691663661076426633273873255729
    Line 134191, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 69846974383 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 69846974383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 8 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 8 failures.
  - 31.otp_ctrl_stress_all_with_rand_reset.114570242068171004070036132771457361973785310060260473617682561395495532855513
    Line 492, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1924564948 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (439430661 [0x1a312e05] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 1924564948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 39.otp_ctrl_stress_all_with_rand_reset.29132317744579785137569148305371388160955661674951735760730441301685211710475
    Line 21833, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 35152927664 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3749823915 [0xdf81c5ab] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 35152927664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 2 failures:

Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

12.otp_ctrl_stress_all_with_rand_reset.82162913460447713205296712584293753437296361173875005970555399030762716943392
Line 35481, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 105915417911 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 105915677651 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 105915690638 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 105916041287 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 105916054274 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

24.otp_ctrl_stress_all_with_rand_reset.92385419999265467650482065656452537489520017138916618954302325750233693885403
Line 18319, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 22656800063 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 22657180063 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 22657300063 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 22657780063 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 22657940063 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_scoreboard.sv:672) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr has 1 failures:
- Test otp_ctrl_stress_all has 1 failures.
  - 16.otp_ctrl_stress_all.27969897809171010603461050521663180706908857910080756308212946921078091239644
    Line 96703, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 15041490680 ps: (otp_ctrl_scoreboard.sv:672) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: OtpErr
  UVM_INFO @ 15041490680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 56.otp_ctrl_stress_all_with_rand_reset.12350054181241935452876176960423158468600484510864370571961008220479363667836
    Line 44427, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/56.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 56560123624 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 3304743317 [0xc4fa6195]) dai addr 70c rdata0 readout mismatch
  UVM_INFO @ 56560123624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 57.otp_ctrl_stress_all_with_rand_reset.25911765263695544173611066714511683679468366110071558229645078122817852839328
    Line 9832, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/57.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 57365575886 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 816 [0x330]) dai addr 330 rdata0 readout mismatch
  UVM_INFO @ 57365575886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(cio_test_en_o == *)' has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 69.otp_ctrl_stress_all_with_rand_reset.50887742967411604485308893233690585678455723609996602676363881402446817375109
    Line 6495, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/69.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 10375218339 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 10375218339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```