OTP_CTRL Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: `b33f0bcb4a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.710s	85.946us	1	1	100.00
V1	smoke	otp_ctrl_smoke	24.170s	5.552ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.660s	397.100us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.180s	553.228us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	8.260s	344.591us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	4.850s	123.191us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	5.090s	1.648ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.180s	553.228us	20	20	100.00
		otp_ctrl_csr_aliasing	4.850s	123.191us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.460s	522.133us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.630s	516.514us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	22.130s	793.427us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	7.640s	2.391ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	29.540s	1.364ms	10	10	100.00
		otp_ctrl_check_fail	54.200s	8.080ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	15.450s	4.233ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.991m	15.705ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	54.550s	2.706ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	35.260s	1.380ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	39.550s	14.682ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	55.390s	23.109ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.355m	9.055ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.142m	12.157ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	12.274m	62.931ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.080s	508.648us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.410s	211.790us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	6.580s	317.356us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	6.580s	317.356us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.660s	397.100us	5	5	100.00
		otp_ctrl_csr_rw	2.180s	553.228us	20	20	100.00
		otp_ctrl_csr_aliasing	4.850s	123.191us	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.160s	1.663ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.660s	397.100us	5	5	100.00
		otp_ctrl_csr_rw	2.180s	553.228us	20	20	100.00
		otp_ctrl_csr_aliasing	4.850s	123.191us	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.160s	1.663ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.696m	43.321ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.696m	43.321ms	5	5	100.00
		otp_ctrl_tl_intg_err	22.640s	2.062ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.696m	43.321ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.696m	43.321ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	22.640s	2.062ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	24.170s	5.552ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	24.170s	5.552ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.696m	43.321ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.696m	43.321ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.696m	43.321ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.696m	43.321ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.696m	43.321ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.696m	43.321ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.696m	43.321ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.696m	43.321ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.696m	43.321ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.696m	43.321ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.696m	43.321ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.696m	43.321ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.696m	43.321ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.696m	43.321ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.696m	43.321ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.550s	14.682ms	200	200	100.00
		otp_ctrl_sec_cm	3.696m	43.321ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.550s	14.682ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.550s	14.682ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.550s	14.682ms	200	200	100.00
		otp_ctrl_macro_errs	1.355m	9.055ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.550s	14.682ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.550s	14.682ms	200	200	100.00
		otp_ctrl_sec_cm	3.696m	43.321ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.550s	14.682ms	200	200	100.00
		otp_ctrl_sec_cm	3.696m	43.321ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.550s	14.682ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.550s	14.682ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.550s	14.682ms	200	200	100.00
		otp_ctrl_macro_errs	1.355m	9.055ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.550s	14.682ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.550s	14.682ms	200	200	100.00
		otp_ctrl_sec_cm	3.696m	43.321ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	7.640s	2.391ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	54.200s	8.080ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.991m	15.705ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.991m	15.705ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.991m	15.705ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.991m	15.705ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.991m	15.705ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	24.170s	5.552ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.991m	15.705ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	24.170s	5.552ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.696m	43.321ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	15.450s	4.233ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	24.170s	5.552ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	24.170s	5.552ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.355m	9.055ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.090s	3.052ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	56.182m	1.955s	78	100	78.00
V3		TOTAL			79	101	78.22
		TOTAL			1321	1343	98.36

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.09	93.86	96.62	96.14	92.12	97.29	96.34	93.28

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 11 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 11 failures.
  - 6.otp_ctrl_stress_all_with_rand_reset.19711022234896301088979793066541896566679519204375564685041947195952422967563
    Line 307, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  33789489 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @  33789489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.otp_ctrl_stress_all_with_rand_reset.66903675324225818761034973845674111684442165679319405416272322727538437693379
    Line 20221, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18269815940 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 18269815940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 3 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 3 failures.
  - 10.otp_ctrl_stress_all_with_rand_reset.82516388467404135069128588309742833399338073250765975422139617884769995143401
    Line 49968, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 792679759103 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1504386293 [0x59ab1cf5] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 792679759103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 44.otp_ctrl_stress_all_with_rand_reset.49035664925333051406763034447194617385188521076379770093087014482493028669456
    Line 75588, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 273686263194 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1072522542 [0x3fed652e] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 273686263194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Offending '(cio_test_en_o == *)' has 3 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 3 failures.
  - 50.otp_ctrl_stress_all_with_rand_reset.23949102818430418776759303099156522815991553170749319340789251251578775492830
    Line 30802, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/50.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 79111718740 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 79111718740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 70.otp_ctrl_stress_all_with_rand_reset.85476775884186086809748299272326995763871119546349195740916683889183758347397
    Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/70.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  51130951 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  51130951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 2 failures:

Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

23.otp_ctrl_stress_all_with_rand_reset.94782145629300460168182646978223391016706349223418426920177417783138237357433
Line 15994, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 22893336239 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 22893713787 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 22893795419 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 22894172967 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 22894264803 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

80.otp_ctrl_stress_all_with_rand_reset.14495618856466999792100387225880326138424512767463299477064807586216695022980
Line 26742, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/80.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 390414318443 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 390419151786 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 390420318455 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 390432485146 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 390432651813 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *b* rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 57.otp_ctrl_stress_all_with_rand_reset.33191414887784950819201192091424651265923628288626857909410992509147238442196
    Line 56438, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/57.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 57864889810 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 696 [0x2b8]) dai addr 2b8 rdata0 readout mismatch
  UVM_INFO @ 57864889810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:277) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 82.otp_ctrl_stress_all_with_rand_reset.55175047677732576461183105078771229492912018444823998869777257533922813355863
    Line 88166, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/82.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 83057975744 ps: (otp_ctrl_scoreboard.sv:277) [uvm_test_top.env.scoreboard] Check failed exp_alert != OtpNoAlert (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 83057975744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 92.otp_ctrl_stress_all_with_rand_reset.6628658844672756077816207579816526482199716516977661264064310361014829163529
    Line 51546, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/92.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 31124849248 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1136 [0x470]) dai addr 474 rdata0 readout mismatch
  UVM_INFO @ 31124849248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```