OTP_CTRL Simulation Results

Sunday June 30 2024 23:02:20 UTC

GitHub Revision: `b33f0bcb4a`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 105302396297609026156504164956156290718642058150905320202190590799028860124396

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	2.620s	761.338us	1	1	100.00
V1	smoke	otp_ctrl_smoke	15.780s	4.446ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	3.140s	399.878us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.170s	617.548us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	10.230s	420.583us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	7.750s	2.537ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	3.560s	114.530us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.170s	617.548us	20	20	100.00
		otp_ctrl_csr_aliasing	7.750s	2.537ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	2.120s	541.534us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.660s	498.699us	5	5	100.00
V1		TOTAL			115	116	99.14
V2	dai_access_partition_walk	otp_ctrl_partition_walk	22.820s	9.881ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	7.760s	2.911ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	26.810s	4.166ms	10	10	100.00
		otp_ctrl_check_fail	1.474m	11.396ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	21.830s	5.300ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	53.030s	18.246ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	53.930s	6.908ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	37.420s	11.937ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	43.640s	19.315ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.054m	6.374ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.078m	24.241ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	59.360s	5.919ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	6.051m	71.959ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.250s	579.733us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.590s	559.361us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.370s	321.209us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.370s	321.209us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	3.140s	399.878us	5	5	100.00
		otp_ctrl_csr_rw	2.170s	617.548us	20	20	100.00
		otp_ctrl_csr_aliasing	7.750s	2.537ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.720s	479.329us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	3.140s	399.878us	5	5	100.00
		otp_ctrl_csr_rw	2.170s	617.548us	20	20	100.00
		otp_ctrl_csr_aliasing	7.750s	2.537ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.720s	479.329us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	5.500m	169.644ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	5.500m	169.644ms	5	5	100.00
		otp_ctrl_tl_intg_err	24.380s	4.771ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	5.500m	169.644ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	5.500m	169.644ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	24.380s	4.771ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	15.780s	4.446ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	15.780s	4.446ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	5.500m	169.644ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	5.500m	169.644ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	5.500m	169.644ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	5.500m	169.644ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	5.500m	169.644ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	5.500m	169.644ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	5.500m	169.644ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	5.500m	169.644ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	5.500m	169.644ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	5.500m	169.644ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	5.500m	169.644ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	5.500m	169.644ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	5.500m	169.644ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	5.500m	169.644ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	5.500m	169.644ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.640s	19.315ms	200	200	100.00
		otp_ctrl_sec_cm	5.500m	169.644ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.640s	19.315ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.640s	19.315ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.640s	19.315ms	200	200	100.00
		otp_ctrl_macro_errs	1.078m	24.241ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.640s	19.315ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.640s	19.315ms	200	200	100.00
		otp_ctrl_sec_cm	5.500m	169.644ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.640s	19.315ms	200	200	100.00
		otp_ctrl_sec_cm	5.500m	169.644ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.640s	19.315ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.640s	19.315ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.640s	19.315ms	200	200	100.00
		otp_ctrl_macro_errs	1.078m	24.241ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.640s	19.315ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.640s	19.315ms	200	200	100.00
		otp_ctrl_sec_cm	5.500m	169.644ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	7.760s	2.911ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.474m	11.396ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	53.030s	18.246ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	53.030s	18.246ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	53.030s	18.246ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	53.030s	18.246ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	53.030s	18.246ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	15.780s	4.446ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	53.030s	18.246ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	15.780s	4.446ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	5.500m	169.644ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	21.830s	5.300ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	15.780s	4.446ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	15.780s	4.446ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.078m	24.241ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	17.500s	7.587ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.157h	1.712s	87	100	87.00
V3		TOTAL			88	101	87.13
		TOTAL			1329	1343	98.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.99	93.78	96.37	95.60	92.36	97.10	96.34	93.35

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 6 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 6 failures.
  - 5.otp_ctrl_stress_all_with_rand_reset.28384267168368681246459491400459654802041720871712853357139626423611090092562
    Line 49155, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 131302700322 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1116937236 [0x42931c14] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 131302700322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 46.otp_ctrl_stress_all_with_rand_reset.28551942841413668833760797611913653952888884833907944883666360053784554932533
    Line 54299, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 88681121913 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (23106914 [0x1609562] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 88681121913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 20.otp_ctrl_stress_all_with_rand_reset.57707559895323107244921895590037986283545493815490040532854217613529880556769
    Line 334, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 582876488 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 582876488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 96.otp_ctrl_stress_all_with_rand_reset.41211678909113621105598396040981474732811430223068665489526563134617338416281
    Line 6677, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/96.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 746151461 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 746151461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 31.otp_ctrl_stress_all_with_rand_reset.49305546914272790559396804715496012227958049422753885207281758057657684823684
    Line 87505, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 296142745584 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 296142745584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.otp_ctrl_stress_all_with_rand_reset.45404093844136400904205861427865149780241811291954966013649126438945372823319
    Line 25709, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 261880487761 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 261880487761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(cio_test_en_o == *)' has 1 failures:
- Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 9.otp_ctrl_csr_mem_rw_with_rand_reset.99961884788967910681904878347533955139703516040541980137911842283898601812539
    Line 267, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 110445370 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 110445370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *f* rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 25.otp_ctrl_stress_all_with_rand_reset.9294727827531797577731502112205702821726929681422260362397548140032264778909
    Line 410, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 36936296315 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1016 [0x3f8]) dai addr 3f8 rdata0 readout mismatch
  UVM_INFO @ 36936296315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *d* rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 59.otp_ctrl_stress_all_with_rand_reset.4380224926860533178993238064705214779607272266933487964239770497730161448913
    Line 18701, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/59.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 261976621679 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1609905767 [0x5ff53667]) dai addr 6d8 rdata0 readout mismatch
  UVM_INFO @ 261976621679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 75.otp_ctrl_stress_all_with_rand_reset.93316459813835700540314164658085600816663852853621831282710347542515498039906
    Line 58926, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/75.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 310061617490 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 580 [0x244]) dai addr 244 rdata0 readout mismatch
  UVM_INFO @ 310061617490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

OTP_CTRL Simulation Results

Sunday June 30 2024 23:02:20 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 105302396297609026156504164956156290718642058150905320202190590799028860124396

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `b33f0bcb4a`