OTP_CTRL Simulation Results

Monday July 01 2024 17:07:21 UTC

GitHub Revision: `eb56ef55d0`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 287373712151371957859909226915296476629077008125381265920192201371239303276

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	2.270s	769.142us	1	1	100.00
V1	smoke	otp_ctrl_smoke	25.570s	10.790ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	4.280s	1.529ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.060s	168.795us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	9.720s	573.055us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.740s	735.653us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.320s	1.595ms	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.060s	168.795us	20	20	100.00
		otp_ctrl_csr_aliasing	6.740s	735.653us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.440s	73.290us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.520s	544.046us	5	5	100.00
V1		TOTAL			115	116	99.14
V2	dai_access_partition_walk	otp_ctrl_partition_walk	19.940s	2.395ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.780s	2.416ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	50.490s	15.320ms	10	10	100.00
		otp_ctrl_check_fail	55.100s	18.869ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	11.890s	1.157ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	39.340s	7.329ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	44.200s	5.752ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	27.400s	9.875ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	1.005m	18.410ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.283m	22.188ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.219m	5.078ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.476m	11.378ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	6.139m	33.609ms	49	50	98.00
V2	intr_test	otp_ctrl_intr_test	2.340s	602.228us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.190s	231.116us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.500s	3.015ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.500s	3.015ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	4.280s	1.529ms	5	5	100.00
		otp_ctrl_csr_rw	2.060s	168.795us	20	20	100.00
		otp_ctrl_csr_aliasing	6.740s	735.653us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.460s	175.115us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	4.280s	1.529ms	5	5	100.00
		otp_ctrl_csr_rw	2.060s	168.795us	20	20	100.00
		otp_ctrl_csr_aliasing	6.740s	735.653us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.460s	175.115us	20	20	100.00
V2		TOTAL			1100	1101	99.91
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	5.468m	154.648ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	5.468m	154.648ms	5	5	100.00
		otp_ctrl_tl_intg_err	28.170s	19.088ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	5.468m	154.648ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	5.468m	154.648ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	28.170s	19.088ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	25.570s	10.790ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	25.570s	10.790ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	5.468m	154.648ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	5.468m	154.648ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	5.468m	154.648ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	5.468m	154.648ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	5.468m	154.648ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	5.468m	154.648ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	5.468m	154.648ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	5.468m	154.648ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	5.468m	154.648ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	5.468m	154.648ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	5.468m	154.648ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	5.468m	154.648ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	5.468m	154.648ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	5.468m	154.648ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	5.468m	154.648ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.005m	18.410ms	200	200	100.00
		otp_ctrl_sec_cm	5.468m	154.648ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.005m	18.410ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.005m	18.410ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.005m	18.410ms	200	200	100.00
		otp_ctrl_macro_errs	1.219m	5.078ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.005m	18.410ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.005m	18.410ms	200	200	100.00
		otp_ctrl_sec_cm	5.468m	154.648ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.005m	18.410ms	200	200	100.00
		otp_ctrl_sec_cm	5.468m	154.648ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.005m	18.410ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.005m	18.410ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.005m	18.410ms	200	200	100.00
		otp_ctrl_macro_errs	1.219m	5.078ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.005m	18.410ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.005m	18.410ms	200	200	100.00
		otp_ctrl_sec_cm	5.468m	154.648ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.780s	2.416ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	55.100s	18.869ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	39.340s	7.329ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	39.340s	7.329ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	39.340s	7.329ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	39.340s	7.329ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	39.340s	7.329ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	25.570s	10.790ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	39.340s	7.329ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	25.570s	10.790ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	5.468m	154.648ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	11.890s	1.157ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	25.570s	10.790ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	25.570s	10.790ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.219m	5.078ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	18.320s	5.914ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.653h	2.976s	83	100	83.00
V3		TOTAL			84	101	83.17
		TOTAL			1324	1343	98.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.75	93.81	96.32	95.67	90.69	97.10	96.34	93.28

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 12 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 12 failures.
  - 15.otp_ctrl_stress_all_with_rand_reset.104421602648910392735299891467468105327893673924990489569082700422746802412943
    Line 21317, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 417014560749 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 417014560749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.otp_ctrl_stress_all_with_rand_reset.67063253133053063440840173702854783327555457422289446180487621973974335547695
    Line 9269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12681279111 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 12681279111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 5 failures:

Test otp_ctrl_stress_all_with_rand_reset has 4 failures.

11.otp_ctrl_stress_all_with_rand_reset.115387403043812024402387844557429654614968487041022669781635991024490150947296
Line 91427, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 348659034807 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (611658326 [0x24752a56] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 348659034807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.otp_ctrl_stress_all_with_rand_reset.302394996305438706313846881662248535798012813941955947968366454878369811929
Line 68507, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 40515437335 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (502537574 [0x1df41d66] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 40515437335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test otp_ctrl_stress_all has 1 failures.

14.otp_ctrl_stress_all.74289123495836290410971679172912625806063637717494388262318317977421863434624
Line 65083, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 12731677472 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1133637500 [0x4391ef7c] vs 1939730430 [0x739deffe]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 12731677472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(cio_test_en_o == *)' has 2 failures:
- Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 13.otp_ctrl_csr_mem_rw_with_rand_reset.53211458631410797770619539438717742746725843049176896175360626754150461275680
    Line 267, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  27286757 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  27286757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 33.otp_ctrl_stress_all_with_rand_reset.78301703367077757802903298801517698586028828940432438905137709141297615680013
    Line 50828, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 19375940436 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 19375940436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```