OTP_CTRL Simulation Results

Monday July 01 2024 23:02:26 UTC

GitHub Revision: e9ae10fb42

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81071883735317974084005537723499931298658500385730214730015283368929474034200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.690s	56.043us	1	1	100.00
V1	smoke	otp_ctrl_smoke	15.680s	2.256ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.740s	970.926us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.000s	683.872us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	11.290s	1.257ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	7.610s	3.123ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.650s	1.626ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.000s	683.872us	20	20	100.00
		otp_ctrl_csr_aliasing	7.610s	3.123ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.680s	555.440us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.390s	35.994us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	20.150s	629.316us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.230s	2.755ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	39.800s	7.557ms	10	10	100.00
		otp_ctrl_check_fail	2.022m	14.658ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	15.730s	4.812ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	50.020s	5.200ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.186m	3.128ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	34.460s	10.890ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	46.860s	5.453ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	50.390s	15.716ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.393m	6.609ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	48.300s	17.604ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	6.077m	24.911ms	49	50	98.00
V2	intr_test	otp_ctrl_intr_test	2.030s	633.069us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.080s	215.856us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	8.820s	2.487ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	8.820s	2.487ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.740s	970.926us	5	5	100.00
		otp_ctrl_csr_rw	2.000s	683.872us	20	20	100.00
		otp_ctrl_csr_aliasing	7.610s	3.123ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.860s	294.253us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.740s	970.926us	5	5	100.00
		otp_ctrl_csr_rw	2.000s	683.872us	20	20	100.00
		otp_ctrl_csr_aliasing	7.610s	3.123ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.860s	294.253us	20	20	100.00
V2		TOTAL			1100	1101	99.91
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.394m	14.444ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.394m	14.444ms	5	5	100.00
		otp_ctrl_tl_intg_err	37.400s	19.843ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.394m	14.444ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.394m	14.444ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	37.400s	19.843ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	15.680s	2.256ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	15.680s	2.256ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.394m	14.444ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.394m	14.444ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.394m	14.444ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.394m	14.444ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.394m	14.444ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.394m	14.444ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.394m	14.444ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.394m	14.444ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.394m	14.444ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.394m	14.444ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.394m	14.444ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.394m	14.444ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.394m	14.444ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.394m	14.444ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.394m	14.444ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	46.860s	5.453ms	200	200	100.00
		otp_ctrl_sec_cm	3.394m	14.444ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	46.860s	5.453ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	46.860s	5.453ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	46.860s	5.453ms	200	200	100.00
		otp_ctrl_macro_errs	1.393m	6.609ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	46.860s	5.453ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	46.860s	5.453ms	200	200	100.00
		otp_ctrl_sec_cm	3.394m	14.444ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	46.860s	5.453ms	200	200	100.00
		otp_ctrl_sec_cm	3.394m	14.444ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	46.860s	5.453ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	46.860s	5.453ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	46.860s	5.453ms	200	200	100.00
		otp_ctrl_macro_errs	1.393m	6.609ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	46.860s	5.453ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	46.860s	5.453ms	200	200	100.00
		otp_ctrl_sec_cm	3.394m	14.444ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.230s	2.755ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	2.022m	14.658ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	50.020s	5.200ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	50.020s	5.200ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	50.020s	5.200ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	50.020s	5.200ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	50.020s	5.200ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	15.680s	2.256ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	50.020s	5.200ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	15.680s	2.256ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.394m	14.444ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	15.730s	4.812ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	15.680s	2.256ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	15.680s	2.256ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.393m	6.609ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	16.100s	5.904ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.201h	1.962s	80	100	80.00
V3		TOTAL			81	101	80.20
		TOTAL			1322	1343	98.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.70	93.81	96.30	95.57	90.45	97.10	96.34	93.35

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 12 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 12 failures.

    • 7.otp_ctrl_stress_all_with_rand_reset.90127366307131281554279197276235164066169251475889446028050355266557380993438
      Line 11095, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10239335077 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 10239335077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 10.otp_ctrl_stress_all_with_rand_reset.108630694135373480156126979097126543982989296167949747655780293338532414564297
      Line 32891, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 23269220167 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 23269220167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 10 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 4 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 4 failures.

    • 22.otp_ctrl_stress_all_with_rand_reset.29177537624837087196477596973631896034598295157424601437874042189917882413127
      Line 1099, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 201581710 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3647992421 [0xd96ff265] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 201581710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 24.otp_ctrl_stress_all_with_rand_reset.54444526285286891945291745726314221206366072810051859824602086728018961900690
      Line 50258, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 40549337644 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3050733159 [0xb5d67e67] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 40549337644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:608) [scoreboard] Check failed item.d_data == otp_a[otp_addr] (* [*] vs * [*]) mem read mismatch at TLUL addr *c64de*, csr_addr * has 1 failures:

  • Test otp_ctrl_stress_all has 1 failures.

    • 35.otp_ctrl_stress_all.10281144577143408940782406311719347031238754663406426909745144732185760643656
      Line 2696, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 341898874 ps: (otp_ctrl_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed item.d_data == otp_a[otp_addr] (4051152511 [0xf177ae7f] vs 561154655 [0x21728a5f]) mem read mismatch at TLUL addr 5c64de70, csr_addr 670
        UVM_INFO @ 341898874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(cio_test_en_o == *)' has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 44.otp_ctrl_stress_all_with_rand_reset.42225245254806620165953580194438829633151739744873611586191776894632851063783
      Line 40495, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 201184605762 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 201184605762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 50.otp_ctrl_stress_all_with_rand_reset.109330246048102673162276153245502593268425262412142297453745192630297188208811
      Line 4154, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/50.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 183500328 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 183500328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 62.otp_ctrl_stress_all_with_rand_reset.54181223140089727363339783626337934374910294644720709000029317815119487795162
      Line 11762, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/62.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 41963252675 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 3894029334 [0xe81a2c16]) dai addr 774 rdata0 readout mismatch
        UVM_INFO @ 41963252675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *d* rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 84.otp_ctrl_stress_all_with_rand_reset.16959518838940507439676604748736923587725387272711283551922720341002581374246
      Line 28931, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/84.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 192780093982 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 728 [0x2d8]) dai addr 2d8 rdata0 readout mismatch
        UVM_INFO @ 192780093982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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