OTP_CTRL Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: `abd7ce57f2`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.810s	184.380us	1	1	100.00
V1	smoke	otp_ctrl_smoke	19.630s	7.345ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.260s	260.592us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.840s	703.240us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	6.450s	3.762ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	5.840s	351.761us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	5.030s	1.800ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.840s	703.240us	20	20	100.00
		otp_ctrl_csr_aliasing	5.840s	351.761us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.440s	519.529us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.370s	139.880us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	19.620s	1.442ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	9.590s	3.397ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	1.246m	7.314ms	10	10	100.00
		otp_ctrl_check_fail	54.970s	4.464ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	16.560s	5.042ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	37.570s	4.401ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	48.990s	2.113ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	32.970s	956.221us	50	50	100.00
		otp_ctrl_parallel_lc_esc	1.017m	21.127ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	51.740s	17.129ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	2.583m	14.364ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	51.880s	7.051ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	4.680m	20.370ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	1.970s	541.078us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	5.320s	604.292us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	6.980s	343.368us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	6.980s	343.368us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.260s	260.592us	5	5	100.00
		otp_ctrl_csr_rw	1.840s	703.240us	20	20	100.00
		otp_ctrl_csr_aliasing	5.840s	351.761us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.260s	1.257ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.260s	260.592us	5	5	100.00
		otp_ctrl_csr_rw	1.840s	703.240us	20	20	100.00
		otp_ctrl_csr_aliasing	5.840s	351.761us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.260s	1.257ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	6.084m	172.742ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	6.084m	172.742ms	5	5	100.00
		otp_ctrl_tl_intg_err	47.010s	20.085ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	6.084m	172.742ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	6.084m	172.742ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	47.010s	20.085ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	19.630s	7.345ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	19.630s	7.345ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	6.084m	172.742ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	6.084m	172.742ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	6.084m	172.742ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	6.084m	172.742ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	6.084m	172.742ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	6.084m	172.742ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	6.084m	172.742ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	6.084m	172.742ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	6.084m	172.742ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	6.084m	172.742ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	6.084m	172.742ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	6.084m	172.742ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	6.084m	172.742ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	6.084m	172.742ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	6.084m	172.742ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.017m	21.127ms	200	200	100.00
		otp_ctrl_sec_cm	6.084m	172.742ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.017m	21.127ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.017m	21.127ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.017m	21.127ms	200	200	100.00
		otp_ctrl_macro_errs	2.583m	14.364ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.017m	21.127ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.017m	21.127ms	200	200	100.00
		otp_ctrl_sec_cm	6.084m	172.742ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.017m	21.127ms	200	200	100.00
		otp_ctrl_sec_cm	6.084m	172.742ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.017m	21.127ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.017m	21.127ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.017m	21.127ms	200	200	100.00
		otp_ctrl_macro_errs	2.583m	14.364ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.017m	21.127ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.017m	21.127ms	200	200	100.00
		otp_ctrl_sec_cm	6.084m	172.742ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	9.590s	3.397ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	54.970s	4.464ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	37.570s	4.401ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	37.570s	4.401ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	37.570s	4.401ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	37.570s	4.401ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	37.570s	4.401ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	19.630s	7.345ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	37.570s	4.401ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	19.630s	7.345ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	6.084m	172.742ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	16.560s	5.042ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	19.630s	7.345ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	19.630s	7.345ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	2.583m	14.364ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.340s	3.007ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.006h	297.652ms	75	100	75.00
V3		TOTAL			76	101	75.25
		TOTAL			1318	1343	98.14

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.92	93.81	96.20	95.72	91.89	97.10	96.34	93.35

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 9 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 9 failures.
  - 3.otp_ctrl_stress_all_with_rand_reset.9894158289995950096245311075755128153868158050412776037552177832728066568224
    Line 29142, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 25109624810 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 25109624810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.otp_ctrl_stress_all_with_rand_reset.34968726560191917642161189645901483005601807014108832031699286096699990108792
    Line 15634, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 27305238175 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 27305238175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 5 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 5 failures.
  - 11.otp_ctrl_stress_all_with_rand_reset.20157579293473601636319447347499520135617818834896062192129039256838903710296
    Line 5940, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 624294130 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3773184490 [0xe0e639ea] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 624294130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.otp_ctrl_stress_all_with_rand_reset.39732097980420634053308481235007529257996694475163338327529428266850756609618
    Line 63340, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 27217959470 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1578582062 [0x5e17402e] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 27217959470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 3 failures:

Test otp_ctrl_stress_all_with_rand_reset has 3 failures.

7.otp_ctrl_stress_all_with_rand_reset.47575651164515368161591038615197063424516797021809001327357909788907341617148
Line 723, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 203952340 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 204012340 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 204032340 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 204352340 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 204372340 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

56.otp_ctrl_stress_all_with_rand_reset.58280851874239492098882561754746447368155744176770509474685291468251103119447
Line 3957, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/56.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 10964378544 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 10965618544 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 10965858544 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 10967938544 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 10967978544 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

... and 1 more failures.

Offending '(cio_test_en_o == *)' has 3 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 3 failures.
  - 18.otp_ctrl_stress_all_with_rand_reset.35403336751196692373562679861450490643250550523977813309898901366482431153199
    Line 34860, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 60193147830 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 60193147830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 48.otp_ctrl_stress_all_with_rand_reset.41765572652269633089551681423463005929380939121332676105047284286906664080198
    Line 11044, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 322331661435 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 322331661435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 14.otp_ctrl_stress_all_with_rand_reset.33841447117110199381867776960866076964399072508430832382525921102600585607718
    Line 23196, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 37928149593 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 37928149593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr c rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 35.otp_ctrl_stress_all_with_rand_reset.98198225330815855066673777935819142150864563154282069665561035793817442703248
    Line 20720, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16368595487 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 12 [0xc]) dai addr c rdata0 readout mismatch
  UVM_INFO @ 16368595487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 38.otp_ctrl_stress_all_with_rand_reset.23876457806370607506760441858977878084769208401647304288805461779291062412534
    Line 20302, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/38.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13861632699 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 872 [0x368]) dai addr 368 rdata0 readout mismatch
  UVM_INFO @ 13861632699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:925) [scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (* [*] vs * [*]) reg name: status, compare_mask * has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 49.otp_ctrl_stress_all_with_rand_reset.39385003250247089166420930570139371184813284523501773268377127402799546564852
    Line 35672, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 178824574134 ps: (otp_ctrl_scoreboard.sv:925) [uvm_test_top.env.scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (268303 [0x4180f] vs 268295 [0x41807]) reg name: status, compare_mask 1000
  UVM_INFO @ 178824574134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 84.otp_ctrl_stress_all_with_rand_reset.41884233768172847807888213081207344090370864293124916451095428887953090123024
    Line 6081, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/84.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 30283540499 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 28 [0x1c]) dai addr 1c rdata0 readout mismatch
  UVM_INFO @ 30283540499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```