OTP_CTRL Simulation Results

Wednesday July 03 2024 23:02:32 UTC

GitHub Revision: `e6706fcc7b`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 8083624550445280117614176890238357255195852125596561370221115831648066795492

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.740s	62.700us	1	1	100.00
V1	smoke	otp_ctrl_smoke	47.710s	6.175ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.440s	107.439us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.450s	656.097us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	9.610s	577.257us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	5.880s	1.203ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.540s	1.637ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.450s	656.097us	20	20	100.00
		otp_ctrl_csr_aliasing	5.880s	1.203ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.850s	520.916us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.480s	135.150us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	19.800s	317.618us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.620s	2.809ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	1.065m	8.360ms	10	10	100.00
		otp_ctrl_check_fail	1.132m	23.692ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	18.100s	4.620ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	51.410s	25.974ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.294m	4.241ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	28.790s	3.510ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	41.750s	21.900ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	44.340s	1.568ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	52.680s	21.516ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	11.285m	94.730ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	6.315m	143.938ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	1.950s	551.796us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	5.000s	529.639us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	8.730s	3.212ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	8.730s	3.212ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.440s	107.439us	5	5	100.00
		otp_ctrl_csr_rw	2.450s	656.097us	20	20	100.00
		otp_ctrl_csr_aliasing	5.880s	1.203ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.750s	1.453ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.440s	107.439us	5	5	100.00
		otp_ctrl_csr_rw	2.450s	656.097us	20	20	100.00
		otp_ctrl_csr_aliasing	5.880s	1.203ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.750s	1.453ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	6.045m	154.706ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	6.045m	154.706ms	5	5	100.00
		otp_ctrl_tl_intg_err	41.390s	20.090ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	6.045m	154.706ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	6.045m	154.706ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	41.390s	20.090ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	47.710s	6.175ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	47.710s	6.175ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	6.045m	154.706ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	6.045m	154.706ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	6.045m	154.706ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	6.045m	154.706ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	6.045m	154.706ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	6.045m	154.706ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	6.045m	154.706ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	6.045m	154.706ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	6.045m	154.706ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	6.045m	154.706ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	6.045m	154.706ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	6.045m	154.706ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	6.045m	154.706ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	6.045m	154.706ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	6.045m	154.706ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.750s	21.900ms	200	200	100.00
		otp_ctrl_sec_cm	6.045m	154.706ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.750s	21.900ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.750s	21.900ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.750s	21.900ms	200	200	100.00
		otp_ctrl_macro_errs	52.680s	21.516ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.750s	21.900ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.750s	21.900ms	200	200	100.00
		otp_ctrl_sec_cm	6.045m	154.706ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.750s	21.900ms	200	200	100.00
		otp_ctrl_sec_cm	6.045m	154.706ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.750s	21.900ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.750s	21.900ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.750s	21.900ms	200	200	100.00
		otp_ctrl_macro_errs	52.680s	21.516ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.750s	21.900ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.750s	21.900ms	200	200	100.00
		otp_ctrl_sec_cm	6.045m	154.706ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.620s	2.809ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.132m	23.692ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	51.410s	25.974ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	51.410s	25.974ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	51.410s	25.974ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	51.410s	25.974ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	51.410s	25.974ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	47.710s	6.175ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	51.410s	25.974ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	47.710s	6.175ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	6.045m	154.706ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	18.100s	4.620ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	47.710s	6.175ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	47.710s	6.175ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	52.680s	21.516ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	17.310s	6.018ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.084h	337.055ms	85	100	85.00
V3		TOTAL			86	101	85.15
		TOTAL			1328	1343	98.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.88	93.76	96.57	96.06	90.93	97.19	96.34	93.28

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 6 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 6 failures.
  - 9.otp_ctrl_stress_all_with_rand_reset.92227781883843762545832932410315964477987295471852682875730167756545502571991
    Line 7024, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13335086965 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 13335086965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.otp_ctrl_stress_all_with_rand_reset.111893113778089273803494369463248186570818871294467747118743465178348588872193
    Line 18469, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 61772101754 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 61772101754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 6 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 6 failures.
  - 16.otp_ctrl_stress_all_with_rand_reset.51067480617940074574780829324478757378281897060842636267718255511573851325548
    Line 18467, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 175123639967 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3837092820 [0xe4b563d4] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 175123639967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.otp_ctrl_stress_all_with_rand_reset.32214835927042149752867920417332461282499147947283434915267604256991484210815
    Line 22675, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 47504194522 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3412194973 [0xcb61f69d] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 47504194522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 1.otp_ctrl_stress_all_with_rand_reset.2480760005364232887772769772146631930469931293003784335758310706164843041312
    Line 99286, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 85431013903 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1060 [0x424]) dai addr 424 rdata0 readout mismatch
  UVM_INFO @ 85431013903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:749) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 19.otp_ctrl_stress_all_with_rand_reset.10005386919921683888336992946452404077994001190533688469851163379478990066452
    Line 375, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 23559472479 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 23559472479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 33.otp_ctrl_stress_all_with_rand_reset.109528280308237137175170886849694187764277879909734783670227671660510742063052
    Line 11297, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 89786125126 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 89786125126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

OTP_CTRL Simulation Results

Wednesday July 03 2024 23:02:32 UTC

GitHub Revision: e6706fcc7b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 8083624550445280117614176890238357255195852125596561370221115831648066795492

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e6706fcc7b`