OTP_CTRL Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: `3e678c112b`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.730s	49.540us	1	1	100.00
V1	smoke	otp_ctrl_smoke	16.570s	5.458ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.370s	96.543us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.220s	686.342us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	9.650s	853.131us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	7.030s	819.054us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.270s	357.996us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.220s	686.342us	20	20	100.00
		otp_ctrl_csr_aliasing	7.030s	819.054us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.410s	38.969us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.950s	531.947us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	19.000s	2.387ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	7.640s	1.955ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	50.540s	7.169ms	10	10	100.00
		otp_ctrl_check_fail	1.137m	5.125ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	12.920s	1.201ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	57.930s	23.213ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.310m	27.613ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	40.070s	12.659ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	39.480s	15.268ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.139m	23.085ms	49	50	98.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.176m	6.300ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.890m	20.046ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	4.692m	75.996ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	1.970s	508.010us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.950s	834.290us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	10.930s	3.187ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	10.930s	3.187ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.370s	96.543us	5	5	100.00
		otp_ctrl_csr_rw	2.220s	686.342us	20	20	100.00
		otp_ctrl_csr_aliasing	7.030s	819.054us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.620s	1.816ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.370s	96.543us	5	5	100.00
		otp_ctrl_csr_rw	2.220s	686.342us	20	20	100.00
		otp_ctrl_csr_aliasing	7.030s	819.054us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.620s	1.816ms	20	20	100.00
V2		TOTAL			1100	1101	99.91
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.666m	37.160ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.666m	37.160ms	5	5	100.00
		otp_ctrl_tl_intg_err	36.430s	20.063ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.666m	37.160ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.666m	37.160ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	36.430s	20.063ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	16.570s	5.458ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	16.570s	5.458ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.666m	37.160ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.666m	37.160ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.666m	37.160ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.666m	37.160ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.666m	37.160ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.666m	37.160ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.666m	37.160ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.666m	37.160ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.666m	37.160ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.666m	37.160ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.666m	37.160ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.666m	37.160ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.666m	37.160ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.666m	37.160ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.666m	37.160ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.480s	15.268ms	200	200	100.00
		otp_ctrl_sec_cm	3.666m	37.160ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.480s	15.268ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.480s	15.268ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.480s	15.268ms	200	200	100.00
		otp_ctrl_macro_errs	1.176m	6.300ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.480s	15.268ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.480s	15.268ms	200	200	100.00
		otp_ctrl_sec_cm	3.666m	37.160ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.480s	15.268ms	200	200	100.00
		otp_ctrl_sec_cm	3.666m	37.160ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.480s	15.268ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.480s	15.268ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.480s	15.268ms	200	200	100.00
		otp_ctrl_macro_errs	1.176m	6.300ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.480s	15.268ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.480s	15.268ms	200	200	100.00
		otp_ctrl_sec_cm	3.666m	37.160ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	7.640s	1.955ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.137m	5.125ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	57.930s	23.213ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	57.930s	23.213ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	57.930s	23.213ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	57.930s	23.213ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	57.930s	23.213ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	16.570s	5.458ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	57.930s	23.213ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	16.570s	5.458ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.666m	37.160ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	12.920s	1.201ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	16.570s	5.458ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	16.570s	5.458ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.176m	6.300ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	13.200s	3.077ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.142h	269.887ms	86	100	86.00
V3		TOTAL			87	101	86.14
		TOTAL			1328	1343	98.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.06	93.81	96.65	95.98	92.12	97.24	96.34	93.28

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 6 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 6 failures.
  - 14.otp_ctrl_stress_all_with_rand_reset.65470811181624016886670968371863773775669753610238944007952599679385760693469
    Line 70580, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1339275287728 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 1339275287728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 51.otp_ctrl_stress_all_with_rand_reset.71968364012357502037787861353094349134468070593562354823653278713812612512667
    Line 28467, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/51.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 135461855956 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 135461855956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 4 failures:

Test otp_ctrl_stress_all_with_rand_reset has 3 failures.

4.otp_ctrl_stress_all_with_rand_reset.55935057208703717817862298878443817148921949365382021744573286542567519797246
Line 70997, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 711992845196 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2367056015 [0x8d16688f] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 711992845196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

87.otp_ctrl_stress_all_with_rand_reset.71888683893941781270770671735117173962320051862271340101780357472855394882441
Line 72826, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/87.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 81534740805 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3443738109 [0xcd4345fd] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 81534740805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test otp_ctrl_dai_errs has 1 failures.

17.otp_ctrl_dai_errs.107603196010591764114769151279262886324658172015646361803601820253403851759691
Line 1544, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_dai_errs/latest/run.log

  UVM_ERROR @ 931836439 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3899741001 [0xe8715349] vs 4210162667 [0xfaf1fbeb]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 931836439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 2 failures:

Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

48.otp_ctrl_stress_all_with_rand_reset.26199882812287415409894356511405017978378661240205237130015233886000253248348
Line 34456, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 79702038673 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 79702129582 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 79702341703 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 79761220432 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 79761371947 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

63.otp_ctrl_stress_all_with_rand_reset.112337656485581961942871830046549827033338748919555173555347566364851218366034
Line 14734, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/63.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 229238084342 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 229238251009 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 229244584355 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 229244751022 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 229249917699 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

Offending '(cio_test_en_o == *)' has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 52.otp_ctrl_stress_all_with_rand_reset.85456224131349149399505434204143070765693932230553226854243576223004214914720
    Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/52.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 108951490 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 108951490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 95.otp_ctrl_stress_all_with_rand_reset.109103032234366716728902626479091171746116676819335699962864569855700857042121
    Line 4351, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/95.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 19832970774 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 19832970774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 83.otp_ctrl_stress_all_with_rand_reset.30519684021245289223179337741052222803010634172679539356900209931658296676277
    Line 273, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/83.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11474298114 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 2366266448 [0x8d0a5c50]) dai addr 728 rdata0 readout mismatch
  UVM_INFO @ 11474298114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```