OTP_CTRL Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: 9edf84e236

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.920s	98.432us	1	1	100.00
V1	smoke	otp_ctrl_smoke	34.780s	3.902ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.380s	156.421us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.360s	581.095us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	8.970s	815.588us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	5.750s	165.810us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	5.110s	1.691ms	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.360s	581.095us	20	20	100.00
		otp_ctrl_csr_aliasing	5.750s	165.810us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.870s	527.908us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.840s	533.527us	5	5	100.00
V1		TOTAL			115	116	99.14
V2	dai_access_partition_walk	otp_ctrl_partition_walk	19.520s	309.016us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.210s	2.894ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	34.650s	15.470ms	10	10	100.00
		otp_ctrl_check_fail	53.960s	20.707ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	14.950s	4.379ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.444m	16.339ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	48.640s	4.987ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	34.530s	11.114ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	33.940s	17.150ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	58.420s	16.472ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	52.580s	16.012ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.538m	8.876ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	6.089m	149.778ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.370s	568.229us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.300s	935.614us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.210s	1.311ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.210s	1.311ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.380s	156.421us	5	5	100.00
		otp_ctrl_csr_rw	2.360s	581.095us	20	20	100.00
		otp_ctrl_csr_aliasing	5.750s	165.810us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.990s	1.537ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.380s	156.421us	5	5	100.00
		otp_ctrl_csr_rw	2.360s	581.095us	20	20	100.00
		otp_ctrl_csr_aliasing	5.750s	165.810us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.990s	1.537ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.555m	37.337ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.555m	37.337ms	5	5	100.00
		otp_ctrl_tl_intg_err	33.990s	3.606ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.555m	37.337ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.555m	37.337ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	33.990s	3.606ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	34.780s	3.902ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	34.780s	3.902ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.555m	37.337ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.555m	37.337ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.555m	37.337ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.555m	37.337ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.555m	37.337ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.555m	37.337ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.555m	37.337ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.555m	37.337ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.555m	37.337ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.555m	37.337ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.555m	37.337ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.555m	37.337ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.555m	37.337ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.555m	37.337ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.555m	37.337ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	33.940s	17.150ms	200	200	100.00
		otp_ctrl_sec_cm	3.555m	37.337ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	33.940s	17.150ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	33.940s	17.150ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	33.940s	17.150ms	200	200	100.00
		otp_ctrl_macro_errs	52.580s	16.012ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	33.940s	17.150ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	33.940s	17.150ms	200	200	100.00
		otp_ctrl_sec_cm	3.555m	37.337ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	33.940s	17.150ms	200	200	100.00
		otp_ctrl_sec_cm	3.555m	37.337ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	33.940s	17.150ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	33.940s	17.150ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	33.940s	17.150ms	200	200	100.00
		otp_ctrl_macro_errs	52.580s	16.012ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	33.940s	17.150ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	33.940s	17.150ms	200	200	100.00
		otp_ctrl_sec_cm	3.555m	37.337ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.210s	2.894ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	53.960s	20.707ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.444m	16.339ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.444m	16.339ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.444m	16.339ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.444m	16.339ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.444m	16.339ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	34.780s	3.902ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.444m	16.339ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	34.780s	3.902ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.555m	37.337ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	14.950s	4.379ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	34.780s	3.902ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	34.780s	3.902ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	52.580s	16.012ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.210s	3.031ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.297h	2.056s	80	100	80.00
V3		TOTAL			81	101	80.20
		TOTAL			1322	1343	98.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.87	93.76	96.23	95.60	91.89	97.05	96.34	93.21

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 12 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 12 failures.

    • 1.otp_ctrl_stress_all_with_rand_reset.87535384615922758287437109335264648201222793188714066780435975373547088091702
      Line 21104, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7039515236 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 7039515236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.otp_ctrl_stress_all_with_rand_reset.44194965100508366794431213588890492074220965019361826720613763889156528588128
      Line 496, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 150405932 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 150405932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 10 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 5 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 5 failures.

    • 0.otp_ctrl_stress_all_with_rand_reset.101892800268944774616226094715306018724836502433955557860173371033514361458650
      Line 8224, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 51752891133 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4025067441 [0xefe9a7b1] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 51752891133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 14.otp_ctrl_stress_all_with_rand_reset.58279741813731145533399918209541985736547565426235120962037120291945803505051
      Line 100569, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 32067461911 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (848967797 [0x329a3875] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 32067461911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *a* rdata* readout mismatch has 2 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

    • 15.otp_ctrl_stress_all_with_rand_reset.37645153812488203986340196407857785706688067101889235719850657191550308453344
      Line 137728, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 105022880870 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 680 [0x2a8]) dai addr 2a8 rdata0 readout mismatch
        UVM_INFO @ 105022880870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 30.otp_ctrl_stress_all_with_rand_reset.11167136294008380700083238961456081757049823566705777526862982681076796819709
      Line 18241, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 158704470344 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1448 [0x5a8]) dai addr 5a8 rdata0 readout mismatch
        UVM_INFO @ 158704470344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(cio_test_en_o == *)' has 1 failures:

  • Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 13.otp_ctrl_csr_mem_rw_with_rand_reset.75930102438699039355210474811381336748270125666729974566129858782099864713609
      Line 267, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @  53251845 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @  53251845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *bc rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 51.otp_ctrl_stress_all_with_rand_reset.68808479682708704520487946720321220295894683548294151544916834466950781692976
      Line 268, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/51.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 943406435 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 444 [0x1bc]) dai addr 1bc rdata0 readout mismatch
        UVM_INFO @ 943406435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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