OTP_CTRL Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: `c42c47ec2d`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.760s	190.146us	1	1	100.00
V1	smoke	otp_ctrl_smoke	22.910s	7.908ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.650s	1.509ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.230s	594.088us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	9.740s	3.076ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	7.140s	837.354us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.050s	1.657ms	17	20	85.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.230s	594.088us	20	20	100.00
		otp_ctrl_csr_aliasing	7.140s	837.354us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.690s	562.228us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.610s	512.083us	5	5	100.00
V1		TOTAL			113	116	97.41
V2	dai_access_partition_walk	otp_ctrl_partition_walk	20.940s	796.753us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.440s	2.667ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	46.300s	26.427ms	10	10	100.00
		otp_ctrl_check_fail	3.265m	40.439ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	18.500s	5.953ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	59.570s	19.522ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	44.890s	11.634ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	29.980s	1.699ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	33.970s	16.637ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	59.720s	23.949ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.401m	10.219ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	38.160s	2.784ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	7.504m	42.967ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	1.930s	557.676us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	4.870s	407.657us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	9.130s	2.604ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	9.130s	2.604ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.650s	1.509ms	5	5	100.00
		otp_ctrl_csr_rw	2.230s	594.088us	20	20	100.00
		otp_ctrl_csr_aliasing	7.140s	837.354us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.950s	463.182us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.650s	1.509ms	5	5	100.00
		otp_ctrl_csr_rw	2.230s	594.088us	20	20	100.00
		otp_ctrl_csr_aliasing	7.140s	837.354us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.950s	463.182us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.276m	41.645ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.276m	41.645ms	5	5	100.00
		otp_ctrl_tl_intg_err	20.790s	2.408ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.276m	41.645ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.276m	41.645ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	20.790s	2.408ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	22.910s	7.908ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	22.910s	7.908ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.276m	41.645ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.276m	41.645ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.276m	41.645ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.276m	41.645ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.276m	41.645ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.276m	41.645ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.276m	41.645ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.276m	41.645ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.276m	41.645ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.276m	41.645ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.276m	41.645ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.276m	41.645ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.276m	41.645ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.276m	41.645ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.276m	41.645ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	33.970s	16.637ms	200	200	100.00
		otp_ctrl_sec_cm	4.276m	41.645ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	33.970s	16.637ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	33.970s	16.637ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	33.970s	16.637ms	200	200	100.00
		otp_ctrl_macro_errs	1.401m	10.219ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	33.970s	16.637ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	33.970s	16.637ms	200	200	100.00
		otp_ctrl_sec_cm	4.276m	41.645ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	33.970s	16.637ms	200	200	100.00
		otp_ctrl_sec_cm	4.276m	41.645ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	33.970s	16.637ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	33.970s	16.637ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	33.970s	16.637ms	200	200	100.00
		otp_ctrl_macro_errs	1.401m	10.219ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	33.970s	16.637ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	33.970s	16.637ms	200	200	100.00
		otp_ctrl_sec_cm	4.276m	41.645ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.440s	2.667ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	3.265m	40.439ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	59.570s	19.522ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	59.570s	19.522ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	59.570s	19.522ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	59.570s	19.522ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	59.570s	19.522ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	22.910s	7.908ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	59.570s	19.522ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	22.910s	7.908ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.276m	41.645ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	18.500s	5.953ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	22.910s	7.908ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	22.910s	7.908ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.401m	10.219ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.630s	3.010ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.011h	1.520s	74	100	74.00
V3		TOTAL			75	101	74.26
		TOTAL			1314	1343	97.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.08	93.81	96.75	96.02	92.12	97.24	96.34	93.28

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 10 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 10 failures.
  - 2.otp_ctrl_stress_all_with_rand_reset.35767442483576181986252486728167399523909210976585658935737288123504277571569
    Line 29224, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 38892894881 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 38892894881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 25.otp_ctrl_stress_all_with_rand_reset.6182680443077077061394017255482922368675815815218748660906779235608051407153
    Line 326, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  72581170 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @  72581170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 9 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 9 failures.
  - 5.otp_ctrl_stress_all_with_rand_reset.54796736720881542681606824449408370769178904052747462721826212905513956261757
    Line 19919, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 64676666363 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2256177158 [0x867a8806] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 64676666363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.otp_ctrl_stress_all_with_rand_reset.87296587432896516307276731750361672569645827781842470932277490240196282157735
    Line 330, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 611131403 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (942594907 [0x382edb5b] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 611131403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
Offending '(cio_test_en_o == *)' has 3 failures:
- Test otp_ctrl_csr_mem_rw_with_rand_reset has 3 failures.
  - 1.otp_ctrl_csr_mem_rw_with_rand_reset.53209173820619900858739893435953377222865688580371419456713175794664347762342
    Line 267, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  26481668 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  26481668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 2.otp_ctrl_csr_mem_rw_with_rand_reset.51632397265587006017059428298196530483143274665095113311811293683938735860154
    Line 267, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  53049437 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  53049437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 55.otp_ctrl_stress_all_with_rand_reset.112878014525870172437440887928388466128328268296514463522793768072062037575566
    Line 87633, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/55.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15155042077 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 15155042077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 98.otp_ctrl_stress_all_with_rand_reset.68203820361462264736262399008237225832941800316998103570694787570869187759989
    Line 18092, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/98.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 55542464227 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 55542464227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 58.otp_ctrl_stress_all_with_rand_reset.16755365794658973961205201621028926423457845950121748404235194892819038499981
    Line 33527, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/58.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 63890154263 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1648 [0x670]) dai addr 674 rdata0 readout mismatch
  UVM_INFO @ 63890154263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 80.otp_ctrl_stress_all_with_rand_reset.102584316782884511429088728827917054830328148319981765496802704036746172633724
    Line 53115, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/80.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 132526035331 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 64 [0x40]) dai addr 40 rdata0 readout mismatch
  UVM_INFO @ 132526035331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 39.otp_ctrl_stress_all_with_rand_reset.39486234482088185783493410754581709984640927935625525390092917549548869816458
    Line 17924, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15623451649 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 56 [0x38]) dai addr 3c rdata0 readout mismatch
  UVM_INFO @ 15623451649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

45.otp_ctrl_stress_all_with_rand_reset.73610212737946748875600591679735313440998487644693711109226047236971273610754
Line 5334, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 1076524219 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 1076681083 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 1077151675 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 1077347755 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 1077759523 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_scoreboard.sv:277) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 63.otp_ctrl_stress_all_with_rand_reset.10633635989671757097116313428253708617049585516434125001956994560919283959864
    Line 5483, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/63.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1773782994 ps: (otp_ctrl_scoreboard.sv:277) [uvm_test_top.env.scoreboard] Check failed exp_alert != OtpNoAlert (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 1773782994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```