OTP_CTRL Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: `2e5d86c9b5`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.720s	56.128us	1	1	100.00
V1	smoke	otp_ctrl_smoke	17.390s	6.518ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.920s	1.557ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.260s	562.680us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	18.630s	6.986ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.360s	321.355us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	5.190s	1.743ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.260s	562.680us	20	20	100.00
		otp_ctrl_csr_aliasing	6.360s	321.355us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	2.030s	557.228us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.420s	65.692us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	23.110s	11.659ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	9.430s	3.120ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	37.550s	4.549ms	10	10	100.00
		otp_ctrl_check_fail	1.520m	11.756ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	20.770s	5.951ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	46.400s	6.295ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	54.340s	18.141ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	35.390s	12.665ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	44.470s	14.119ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	55.310s	6.103ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	53.260s	2.516ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.148m	8.628ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	5.362m	55.071ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.260s	613.072us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	4.020s	372.629us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	9.040s	2.631ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	9.040s	2.631ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.920s	1.557ms	5	5	100.00
		otp_ctrl_csr_rw	2.260s	562.680us	20	20	100.00
		otp_ctrl_csr_aliasing	6.360s	321.355us	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.530s	1.667ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.920s	1.557ms	5	5	100.00
		otp_ctrl_csr_rw	2.260s	562.680us	20	20	100.00
		otp_ctrl_csr_aliasing	6.360s	321.355us	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.530s	1.667ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.450m	154.671ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.450m	154.671ms	5	5	100.00
		otp_ctrl_tl_intg_err	23.420s	4.965ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.450m	154.671ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.450m	154.671ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	23.420s	4.965ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	17.390s	6.518ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	17.390s	6.518ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.450m	154.671ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.450m	154.671ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.450m	154.671ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.450m	154.671ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.450m	154.671ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.450m	154.671ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.450m	154.671ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.450m	154.671ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.450m	154.671ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.450m	154.671ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.450m	154.671ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.450m	154.671ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.450m	154.671ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.450m	154.671ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.450m	154.671ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	44.470s	14.119ms	200	200	100.00
		otp_ctrl_sec_cm	4.450m	154.671ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	44.470s	14.119ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	44.470s	14.119ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	44.470s	14.119ms	200	200	100.00
		otp_ctrl_macro_errs	53.260s	2.516ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	44.470s	14.119ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	44.470s	14.119ms	200	200	100.00
		otp_ctrl_sec_cm	4.450m	154.671ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	44.470s	14.119ms	200	200	100.00
		otp_ctrl_sec_cm	4.450m	154.671ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	44.470s	14.119ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	44.470s	14.119ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	44.470s	14.119ms	200	200	100.00
		otp_ctrl_macro_errs	53.260s	2.516ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	44.470s	14.119ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	44.470s	14.119ms	200	200	100.00
		otp_ctrl_sec_cm	4.450m	154.671ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	9.430s	3.120ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.520m	11.756ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	46.400s	6.295ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	46.400s	6.295ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	46.400s	6.295ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	46.400s	6.295ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	46.400s	6.295ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	17.390s	6.518ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	46.400s	6.295ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	17.390s	6.518ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.450m	154.671ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	20.770s	5.951ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	17.390s	6.518ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	17.390s	6.518ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	53.260s	2.516ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	11.590s	7.587ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.359h	1.635s	80	100	80.00
V3		TOTAL			81	101	80.20
		TOTAL			1323	1343	98.51

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.96	93.86	96.30	95.59	92.36	96.91	96.34	93.35

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 13 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 13 failures.
  - 9.otp_ctrl_stress_all_with_rand_reset.93629839214387035065850589491581133065917871691685379356477703650836641070467
    Line 3756, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7672292637 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 7672292637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.otp_ctrl_stress_all_with_rand_reset.62297358512670073944912577552740830665562230699451427836196193347199932907974
    Line 516, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6532174232 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 6532174232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 5 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 5 failures.
  - 3.otp_ctrl_stress_all_with_rand_reset.73749158328969056778720228295642405526193150874415586551139465996854291514135
    Line 11637, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 155588473343 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1673551128 [0x63c05d18] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 155588473343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.otp_ctrl_stress_all_with_rand_reset.101592073537001510466022440050643462555390132901004970870319291308720173253767
    Line 7840, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 145813426290 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (143199086 [0x8890b6e] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 145813426290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:277) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 31.otp_ctrl_stress_all_with_rand_reset.13326913628179231639522721907933557114794068421164251039228041273113506056095
    Line 5016, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 21504320000 ps: (otp_ctrl_scoreboard.sv:277) [uvm_test_top.env.scoreboard] Check failed exp_alert != OtpNoAlert (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 21504320000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(cio_test_en_o == *)' has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 37.otp_ctrl_stress_all_with_rand_reset.58557098931285558771926480132890826338189783184936936007161775698712357497313
    Line 27356, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 452103844563 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 452103844563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

OTP_CTRL Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: 2e5d86c9b5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `2e5d86c9b5`