OTP_CTRL Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: `6a84251492`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.710s	193.375us	1	1	100.00
V1	smoke	otp_ctrl_smoke	16.680s	7.071ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.900s	386.725us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.100s	566.975us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	8.970s	349.049us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	9.500s	2.543ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.480s	110.545us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.100s	566.975us	20	20	100.00
		otp_ctrl_csr_aliasing	9.500s	2.543ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.430s	71.076us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.550s	518.781us	5	5	100.00
V1		TOTAL			115	116	99.14
V2	dai_access_partition_walk	otp_ctrl_partition_walk	23.410s	3.072ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.440s	2.028ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	33.080s	3.136ms	10	10	100.00
		otp_ctrl_check_fail	1.090m	8.667ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	12.440s	517.236us	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.617m	31.147ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.068m	3.088ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	37.820s	13.286ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	32.310s	14.853ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	46.730s	6.123ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.151m	15.019ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.115m	8.727ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	8.724m	70.190ms	49	50	98.00
V2	intr_test	otp_ctrl_intr_test	2.100s	613.071us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.710s	332.857us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	9.160s	2.687ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	9.160s	2.687ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.900s	386.725us	5	5	100.00
		otp_ctrl_csr_rw	2.100s	566.975us	20	20	100.00
		otp_ctrl_csr_aliasing	9.500s	2.543ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.830s	127.989us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.900s	386.725us	5	5	100.00
		otp_ctrl_csr_rw	2.100s	566.975us	20	20	100.00
		otp_ctrl_csr_aliasing	9.500s	2.543ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.830s	127.989us	20	20	100.00
V2		TOTAL			1100	1101	99.91
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.871m	173.167ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.871m	173.167ms	5	5	100.00
		otp_ctrl_tl_intg_err	48.270s	18.894ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.871m	173.167ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.871m	173.167ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	48.270s	18.894ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	16.680s	7.071ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	16.680s	7.071ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.871m	173.167ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.871m	173.167ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.871m	173.167ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.871m	173.167ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.871m	173.167ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.871m	173.167ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.871m	173.167ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.871m	173.167ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.871m	173.167ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.871m	173.167ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.871m	173.167ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.871m	173.167ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.871m	173.167ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.871m	173.167ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.871m	173.167ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.310s	14.853ms	200	200	100.00
		otp_ctrl_sec_cm	4.871m	173.167ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.310s	14.853ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.310s	14.853ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.310s	14.853ms	200	200	100.00
		otp_ctrl_macro_errs	1.151m	15.019ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.310s	14.853ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.310s	14.853ms	200	200	100.00
		otp_ctrl_sec_cm	4.871m	173.167ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.310s	14.853ms	200	200	100.00
		otp_ctrl_sec_cm	4.871m	173.167ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.310s	14.853ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.310s	14.853ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.310s	14.853ms	200	200	100.00
		otp_ctrl_macro_errs	1.151m	15.019ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.310s	14.853ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.310s	14.853ms	200	200	100.00
		otp_ctrl_sec_cm	4.871m	173.167ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.440s	2.028ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.090m	8.667ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.617m	31.147ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.617m	31.147ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.617m	31.147ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.617m	31.147ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.617m	31.147ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	16.680s	7.071ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.617m	31.147ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	16.680s	7.071ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.871m	173.167ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	12.440s	517.236us	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	16.680s	7.071ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	16.680s	7.071ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.151m	15.019ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	16.590s	6.976ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.193h	1.704s	86	100	86.00
V3		TOTAL			87	101	86.14
		TOTAL			1327	1343	98.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.02	93.87	96.75	95.89	91.65	97.29	96.34	93.35

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 7 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 7 failures.
  - 5.otp_ctrl_stress_all_with_rand_reset.57416514908966565687197113689139622814276787326114343358908170816684618150726
    Line 317, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 572110482 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 572110482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.otp_ctrl_stress_all_with_rand_reset.33530071293946784384824087240843378708552532989341243261871700061484045769748
    Line 6509, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 237897465 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 237897465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 5 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 5 failures.
  - 18.otp_ctrl_stress_all_with_rand_reset.3962016396252118647283400170403880563262818203668523541020564362696342740269
    Line 19396, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 25675111752 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2757782250 [0xa4606aea] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 25675111752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 37.otp_ctrl_stress_all_with_rand_reset.71531281504540878027737444825798988808917517906577539306410569847072083412407
    Line 24920, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15223361839 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (866732017 [0x33a947f1] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 15223361839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
Offending '(cio_test_en_o == *)' has 2 failures:
- Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 7.otp_ctrl_csr_mem_rw_with_rand_reset.67942810326550547591773191630947296624147426285634644511645002136359407767396
    Line 276, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  58693175 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  58693175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 28.otp_ctrl_stress_all_with_rand_reset.29205818571372830490285234993494161667188426152747025597363370766031467396871
    Line 33774, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 157822691260 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 157822691260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:608) [scoreboard] Check failed item.d_data == otp_a[otp_addr] (* [*] vs * [*]) mem read mismatch at TLUL addr *a3c0c*, csr_addr * has 1 failures:
- Test otp_ctrl_stress_all has 1 failures.
  - 35.otp_ctrl_stress_all.80862791950450696674711378806595095582744072652415702561704146950336626105684
    Line 96226, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 10396478680 ps: (otp_ctrl_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed item.d_data == otp_a[otp_addr] (1061092237 [0x3f3efb8d] vs 824375561 [0x3122f909]) mem read mismatch at TLUL addr 7a3c0c70, csr_addr 470
  UVM_INFO @ 10396478680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

39.otp_ctrl_stress_all_with_rand_reset.38365324412944626539618584282050912719677168736369167265904552388668075788134
Line 83694, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 342499866270 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 342500991279 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 342501032946 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 342502449624 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 342502491291 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1