OTP_CTRL Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: `39211701b5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.620s	101.243us	1	1	100.00
V1	smoke	otp_ctrl_smoke	18.920s	6.870ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	3.810s	1.506ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.030s	678.331us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	11.240s	6.962ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.700s	409.205us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.600s	1.657ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.030s	678.331us	20	20	100.00
		otp_ctrl_csr_aliasing	6.700s	409.205us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.550s	138.314us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.730s	515.968us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	17.940s	2.268ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	9.520s	2.459ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	48.390s	15.698ms	10	10	100.00
		otp_ctrl_check_fail	2.082m	32.453ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	14.480s	4.717ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.716m	21.188ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.054m	30.172ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	36.100s	9.737ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	40.270s	1.420ms	198	200	99.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.004m	14.694ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.028m	16.337ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.294m	16.084ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	6.263m	98.659ms	49	50	98.00
V2	intr_test	otp_ctrl_intr_test	2.130s	548.211us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.130s	1.104ms	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.300s	176.276us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.300s	176.276us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	3.810s	1.506ms	5	5	100.00
		otp_ctrl_csr_rw	2.030s	678.331us	20	20	100.00
		otp_ctrl_csr_aliasing	6.700s	409.205us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.380s	1.603ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	3.810s	1.506ms	5	5	100.00
		otp_ctrl_csr_rw	2.030s	678.331us	20	20	100.00
		otp_ctrl_csr_aliasing	6.700s	409.205us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.380s	1.603ms	20	20	100.00
V2		TOTAL			1098	1101	99.73
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.359m	21.850ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.359m	21.850ms	5	5	100.00
		otp_ctrl_tl_intg_err	37.960s	20.229ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.359m	21.850ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.359m	21.850ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	37.960s	20.229ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	18.920s	6.870ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	18.920s	6.870ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.359m	21.850ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.359m	21.850ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.359m	21.850ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.359m	21.850ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.359m	21.850ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.359m	21.850ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.359m	21.850ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.359m	21.850ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.359m	21.850ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.359m	21.850ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.359m	21.850ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.359m	21.850ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.359m	21.850ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.359m	21.850ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.359m	21.850ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	40.270s	1.420ms	198	200	99.00
		otp_ctrl_sec_cm	3.359m	21.850ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	40.270s	1.420ms	198	200	99.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	40.270s	1.420ms	198	200	99.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	40.270s	1.420ms	198	200	99.00
		otp_ctrl_macro_errs	1.028m	16.337ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	40.270s	1.420ms	198	200	99.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	40.270s	1.420ms	198	200	99.00
		otp_ctrl_sec_cm	3.359m	21.850ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	40.270s	1.420ms	198	200	99.00
		otp_ctrl_sec_cm	3.359m	21.850ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	40.270s	1.420ms	198	200	99.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	40.270s	1.420ms	198	200	99.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	40.270s	1.420ms	198	200	99.00
		otp_ctrl_macro_errs	1.028m	16.337ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	40.270s	1.420ms	198	200	99.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	40.270s	1.420ms	198	200	99.00
		otp_ctrl_sec_cm	3.359m	21.850ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	9.520s	2.459ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	2.082m	32.453ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.716m	21.188ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.716m	21.188ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.716m	21.188ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.716m	21.188ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.716m	21.188ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	18.920s	6.870ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.716m	21.188ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	18.920s	6.870ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.359m	21.850ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	14.480s	4.717ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	18.920s	6.870ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	18.920s	6.870ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.028m	16.337ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.510s	5.895ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.151h	1.638s	78	100	78.00
V3		TOTAL			79	101	78.22
		TOTAL			1318	1343	98.14

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	15	88.24
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.74	93.76	96.15	95.81	90.93	97.00	96.28	93.28

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 11 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 11 failures.
  - 0.otp_ctrl_stress_all_with_rand_reset.80891376964347757115296719531758577136411421706945384304390726424137277229351
    Line 20079, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1350487903 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 1350487903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.otp_ctrl_stress_all_with_rand_reset.69706581104486721550707645011990481923105347837139613013529902564626055623754
    Line 6486, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12337411044 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 12337411044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 7 failures:

Test otp_ctrl_stress_all has 1 failures.

6.otp_ctrl_stress_all.75619740408400651435195215680957161332096852128098536422297017675203286946606
Line 33954, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 23131524211 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4274294486 [0xfec48ed6] vs 4277002239 [0xfeeddfff]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 23131524211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otp_ctrl_stress_all_with_rand_reset has 6 failures.

39.otp_ctrl_stress_all_with_rand_reset.55017661198714245370467687855356207954778947492851433513843744629690061995054
Line 1406, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 338288531 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1985283739 [0x7655069b] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 338288531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

43.otp_ctrl_stress_all_with_rand_reset.35271659017078953896352833953540032276235383158777739677804963396575279826826
Line 38710, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 62635361200 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2995668193 [0xb28e44e1] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 62635361200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Offending '(cio_test_en_o == *)' has 3 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 3 failures.
  - 11.otp_ctrl_stress_all_with_rand_reset.77580481211142816998405634900035454592837204447730656295454123964504244665233
    Line 320, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 2960050808 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 2960050808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 21.otp_ctrl_stress_all_with_rand_reset.36555116551717549307731376727094333879948555399333809693673031986295955264338
    Line 89329, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 66671751885 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 66671751885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 2 failures:

Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

1.otp_ctrl_stress_all_with_rand_reset.33453519255600721607874533346276554366229678722673818496879406729404230699186
Line 8529, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 15378265245 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 15378765246 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 15378931913 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 15398098618 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 15398265285 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

7.otp_ctrl_stress_all_with_rand_reset.32571185838369723632609560274686591241244236631407879901932430777993297212045
Line 14360, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 46712452816 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 46713536158 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 46713577825 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 46715536174 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 46715577841 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_check_error did not trigger max_delay:* has 2 failures:
- Test otp_ctrl_parallel_lc_esc has 2 failures.
  - 15.otp_ctrl_parallel_lc_esc.104701240547224982797691051301402694153631751947926102400864279810053181754686
    Line 2799, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_esc/latest/run.log
```
  UVM_ERROR @ 152575291 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_check_error did not trigger max_delay:5
  UVM_INFO @ 152575291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 85.otp_ctrl_parallel_lc_esc.19675074151252883630016769160539856281255055410637886482684847662880255146689
    Line 2833, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/85.otp_ctrl_parallel_lc_esc/latest/run.log
```
  UVM_ERROR @  56895013 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_check_error did not trigger max_delay:5
  UVM_INFO @  56895013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```