OTP_CTRL Simulation Results

Thursday July 11 2024 23:02:31 UTC

GitHub Revision: `edf2fd5092`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 110991919330983905489672005724934609038320729526710604109871030362225161447318

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.650s	53.755us	1	1	100.00
V1	smoke	otp_ctrl_smoke	18.730s	7.002ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.660s	362.620us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.870s	153.866us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	13.280s	6.267ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	7.270s	723.025us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.900s	1.521ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.870s	153.866us	20	20	100.00
		otp_ctrl_csr_aliasing	7.270s	723.025us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.390s	37.751us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.760s	551.126us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	20.020s	1.221ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.200s	2.984ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	38.150s	2.096ms	10	10	100.00
		otp_ctrl_check_fail	49.660s	4.428ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	18.970s	4.368ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.106m	30.013ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.359m	26.254ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	43.130s	12.357ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	33.550s	11.444ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	50.840s	5.431ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.483m	29.694ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	56.430s	9.859ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	5.447m	147.371ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.310s	618.375us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.500s	274.700us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.890s	3.082ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.890s	3.082ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.660s	362.620us	5	5	100.00
		otp_ctrl_csr_rw	1.870s	153.866us	20	20	100.00
		otp_ctrl_csr_aliasing	7.270s	723.025us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.790s	156.268us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.660s	362.620us	5	5	100.00
		otp_ctrl_csr_rw	1.870s	153.866us	20	20	100.00
		otp_ctrl_csr_aliasing	7.270s	723.025us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.790s	156.268us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.668m	154.601ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.668m	154.601ms	5	5	100.00
		otp_ctrl_tl_intg_err	42.540s	19.811ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.668m	154.601ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.668m	154.601ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	42.540s	19.811ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	18.730s	7.002ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	18.730s	7.002ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.668m	154.601ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.668m	154.601ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.668m	154.601ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.668m	154.601ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.668m	154.601ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.668m	154.601ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.668m	154.601ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.668m	154.601ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.668m	154.601ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.668m	154.601ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.668m	154.601ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.668m	154.601ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.668m	154.601ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.668m	154.601ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.668m	154.601ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	33.550s	11.444ms	200	200	100.00
		otp_ctrl_sec_cm	3.668m	154.601ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	33.550s	11.444ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	33.550s	11.444ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	33.550s	11.444ms	200	200	100.00
		otp_ctrl_macro_errs	1.483m	29.694ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	33.550s	11.444ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	33.550s	11.444ms	200	200	100.00
		otp_ctrl_sec_cm	3.668m	154.601ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	33.550s	11.444ms	200	200	100.00
		otp_ctrl_sec_cm	3.668m	154.601ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	33.550s	11.444ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	33.550s	11.444ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	33.550s	11.444ms	200	200	100.00
		otp_ctrl_macro_errs	1.483m	29.694ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	33.550s	11.444ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	33.550s	11.444ms	200	200	100.00
		otp_ctrl_sec_cm	3.668m	154.601ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.200s	2.984ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	49.660s	4.428ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.106m	30.013ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.106m	30.013ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.106m	30.013ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.106m	30.013ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.106m	30.013ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	18.730s	7.002ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.106m	30.013ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	18.730s	7.002ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.668m	154.601ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	18.970s	4.368ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	18.730s	7.002ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	18.730s	7.002ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.483m	29.694ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	13.370s	3.067ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.034h	231.679ms	85	100	85.00
V3		TOTAL			86	101	85.15
		TOTAL			1328	1343	98.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.05	93.81	96.67	96.08	91.89	97.24	96.34	93.35

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 8 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 8 failures.
  - 41.otp_ctrl_stress_all_with_rand_reset.2505931533350955340617505098523032129300831400248852821576739284721090427437
    Line 85684, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 98599461319 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 98599461319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 51.otp_ctrl_stress_all_with_rand_reset.110144175408722150518385051480890937124168647403218225327629554783834484144061
    Line 18870, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/51.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2952772855 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 2952772855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 3 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 3 failures.
  - 28.otp_ctrl_stress_all_with_rand_reset.10941483332745385741856715258236382349526813024148602328552365052159023671463
    Line 328, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  34642909 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (890546163 [0x3514a7f3] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @  34642909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 80.otp_ctrl_stress_all_with_rand_reset.115519205620386289072383429803864117334948527918509616608880781509226178953500
    Line 6926, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/80.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17527499965 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1757372894 [0x68bf61de] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 17527499965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Offending '(cio_test_en_o == *)' has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 94.otp_ctrl_stress_all_with_rand_reset.29379087765396002368256967639775495142965648460712265969108554823313807949988
    Line 492, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/94.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 3025742296 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 3025742296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 96.otp_ctrl_stress_all_with_rand_reset.17400644406385265212058009705939103453486881181814295129329930958088636877954
    Line 14900, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/96.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 37776014484 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 37776014484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

16.otp_ctrl_stress_all_with_rand_reset.73241458372000197952082576937970452271139855509837242948376134575367889754580
Line 14520, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 232054906476 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 232062573158 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 232062739825 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 232068739837 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 232070073173 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 36.otp_ctrl_stress_all_with_rand_reset.15363084498395821496026784880695392124768411923345343307366174437296017165023
    Line 93411, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 56693848831 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 908 [0x38c]) dai addr 38c rdata0 readout mismatch
  UVM_INFO @ 56693848831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```