OTP_CTRL Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: 5967df933a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.770s	103.186us	1	1	100.00
V1	smoke	otp_ctrl_smoke	15.370s	4.552ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.530s	103.305us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.920s	604.460us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	5.880s	267.963us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	5.750s	480.899us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.140s	1.135ms	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.920s	604.460us	20	20	100.00
		otp_ctrl_csr_aliasing	5.750s	480.899us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.960s	532.050us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.810s	543.719us	5	5	100.00
V1		TOTAL			115	116	99.14
V2	dai_access_partition_walk	otp_ctrl_partition_walk	18.890s	530.252us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	9.500s	2.649ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	31.440s	4.756ms	10	10	100.00
		otp_ctrl_check_fail	1.025m	6.296ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	14.700s	5.694ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	55.790s	8.288ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.140m	23.484ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	43.950s	12.665ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	50.090s	14.771ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.051m	23.007ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	2.344m	18.701ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	51.860s	3.856ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	6.278m	50.720ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	1.650s	544.341us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.250s	937.372us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	6.850s	206.444us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	6.850s	206.444us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.530s	103.305us	5	5	100.00
		otp_ctrl_csr_rw	1.920s	604.460us	20	20	100.00
		otp_ctrl_csr_aliasing	5.750s	480.899us	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.050s	1.888ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.530s	103.305us	5	5	100.00
		otp_ctrl_csr_rw	1.920s	604.460us	20	20	100.00
		otp_ctrl_csr_aliasing	5.750s	480.899us	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.050s	1.888ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.461m	38.449ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.461m	38.449ms	5	5	100.00
		otp_ctrl_tl_intg_err	21.580s	2.553ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.461m	38.449ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.461m	38.449ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	21.580s	2.553ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	15.370s	4.552ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	15.370s	4.552ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.461m	38.449ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.461m	38.449ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.461m	38.449ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.461m	38.449ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.461m	38.449ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.461m	38.449ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.461m	38.449ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.461m	38.449ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.461m	38.449ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.461m	38.449ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.461m	38.449ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.461m	38.449ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.461m	38.449ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.461m	38.449ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.461m	38.449ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	50.090s	14.771ms	200	200	100.00
		otp_ctrl_sec_cm	4.461m	38.449ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	50.090s	14.771ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	50.090s	14.771ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	50.090s	14.771ms	200	200	100.00
		otp_ctrl_macro_errs	2.344m	18.701ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	50.090s	14.771ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	50.090s	14.771ms	200	200	100.00
		otp_ctrl_sec_cm	4.461m	38.449ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	50.090s	14.771ms	200	200	100.00
		otp_ctrl_sec_cm	4.461m	38.449ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	50.090s	14.771ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	50.090s	14.771ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	50.090s	14.771ms	200	200	100.00
		otp_ctrl_macro_errs	2.344m	18.701ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	50.090s	14.771ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	50.090s	14.771ms	200	200	100.00
		otp_ctrl_sec_cm	4.461m	38.449ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	9.500s	2.649ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.025m	6.296ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	55.790s	8.288ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	55.790s	8.288ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	55.790s	8.288ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	55.790s	8.288ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	55.790s	8.288ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	15.370s	4.552ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	55.790s	8.288ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	15.370s	4.552ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.461m	38.449ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	14.700s	5.694ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	15.370s	4.552ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	15.370s	4.552ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	2.344m	18.701ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	13.610s	3.399ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.170h	1.560s	83	100	83.00
V3		TOTAL			84	101	83.17
		TOTAL			1325	1343	98.66

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.92	93.76	96.15	95.83	92.12	97.00	96.28	93.28

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 7 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 7 failures.

    • 4.otp_ctrl_stress_all_with_rand_reset.77949678923528746765717288402807977339634341278689087317344954288787902848579
      Line 45425, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 78283178005 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 78283178005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 11.otp_ctrl_stress_all_with_rand_reset.45809686422181969395746431834856351252729378278357152245368338156901175797159
      Line 70677, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1261467804654 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 1261467804654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 6 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 6 failures.

    • 0.otp_ctrl_stress_all_with_rand_reset.105456613356518170787368273205151118172024440921274068366041080286042482897005
      Line 59809, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 758454960710 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2308146641 [0x899385d1] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 758454960710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 27.otp_ctrl_stress_all_with_rand_reset.91361458795412662699232523310144059083037008258236679735102260210994522864053
      Line 95002, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 24136418979 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1214860394 [0x48694c6a] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 24136418979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 4 more failures.

• Offending '(cio_test_en_o == *)' has 3 failures:

  • Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.otp_ctrl_csr_mem_rw_with_rand_reset.61890917506313597775269942923071040471178431544889432847741466389943359062732
      Line 267, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @  51081842 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @  51081842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

    • 82.otp_ctrl_stress_all_with_rand_reset.61888112702291130389485241035216259551864704174514203328751385835849633210188
      Line 61539, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/82.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 235230555001 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 235230555001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 85.otp_ctrl_stress_all_with_rand_reset.45371362674471241684224011296055650558505917874689390050426131244300313413453
      Line 20506, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/85.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 1426002325 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 1426002325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 2 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

    • 32.otp_ctrl_stress_all_with_rand_reset.412430947561958072576181675426698668361806850639746508752045707613643765865
      Line 71190, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 60705739615 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 60705739615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 76.otp_ctrl_stress_all_with_rand_reset.35849677425320515260518801725607360175698989910577432888397374638175408492466
      Line 6964, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/76.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1473073072 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 1473073072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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