OTP_CTRL Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: `d51405297e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.700s	53.600us	1	1	100.00
V1	smoke	otp_ctrl_smoke	33.710s	3.721ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	4.540s	1.582ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.780s	73.008us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	6.950s	1.982ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.010s	346.985us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	5.950s	1.730ms	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.780s	73.008us	20	20	100.00
		otp_ctrl_csr_aliasing	6.010s	346.985us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.780s	527.595us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.490s	133.746us	5	5	100.00
V1		TOTAL			114	116	98.28
V2	dai_access_partition_walk	otp_ctrl_partition_walk	19.820s	1.024ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.430s	2.015ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	43.960s	7.126ms	10	10	100.00
		otp_ctrl_check_fail	1.128m	27.196ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	19.710s	5.578ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	2.118m	17.286ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.592m	10.179ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	31.480s	10.719ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	41.060s	18.305ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	59.700s	24.693ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	56.280s	18.640ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.512m	8.688ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	12.710m	131.610ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.030s	590.064us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.850s	777.737us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.930s	2.846ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.930s	2.846ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	4.540s	1.582ms	5	5	100.00
		otp_ctrl_csr_rw	1.780s	73.008us	20	20	100.00
		otp_ctrl_csr_aliasing	6.010s	346.985us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.810s	2.177ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	4.540s	1.582ms	5	5	100.00
		otp_ctrl_csr_rw	1.780s	73.008us	20	20	100.00
		otp_ctrl_csr_aliasing	6.010s	346.985us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.810s	2.177ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.409m	13.402ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.409m	13.402ms	5	5	100.00
		otp_ctrl_tl_intg_err	34.670s	20.087ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.409m	13.402ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.409m	13.402ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	34.670s	20.087ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	33.710s	3.721ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	33.710s	3.721ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.409m	13.402ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.409m	13.402ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.409m	13.402ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.409m	13.402ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.409m	13.402ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.409m	13.402ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.409m	13.402ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.409m	13.402ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.409m	13.402ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.409m	13.402ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.409m	13.402ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.409m	13.402ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.409m	13.402ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.409m	13.402ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.409m	13.402ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.060s	18.305ms	200	200	100.00
		otp_ctrl_sec_cm	3.409m	13.402ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.060s	18.305ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.060s	18.305ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.060s	18.305ms	200	200	100.00
		otp_ctrl_macro_errs	56.280s	18.640ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.060s	18.305ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.060s	18.305ms	200	200	100.00
		otp_ctrl_sec_cm	3.409m	13.402ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.060s	18.305ms	200	200	100.00
		otp_ctrl_sec_cm	3.409m	13.402ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.060s	18.305ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.060s	18.305ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.060s	18.305ms	200	200	100.00
		otp_ctrl_macro_errs	56.280s	18.640ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.060s	18.305ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.060s	18.305ms	200	200	100.00
		otp_ctrl_sec_cm	3.409m	13.402ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.430s	2.015ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.128m	27.196ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	2.118m	17.286ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	2.118m	17.286ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	2.118m	17.286ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	2.118m	17.286ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	2.118m	17.286ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	33.710s	3.721ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	2.118m	17.286ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	33.710s	3.721ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.409m	13.402ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	19.710s	5.578ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	33.710s	3.721ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	33.710s	3.721ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	56.280s	18.640ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	10.700s	3.051ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.414h	2.203s	81	100	81.00
V3		TOTAL			82	101	81.19
		TOTAL			1322	1343	98.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.92	93.76	96.18	95.67	92.12	97.05	96.34	93.35

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 7 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 7 failures.
  - 37.otp_ctrl_stress_all_with_rand_reset.64430880478854107859241934426656314448572992510898567252929678154789200685974
    Line 43374, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 62145975889 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4260987791 [0xfdf9838f] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 62145975889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 54.otp_ctrl_stress_all_with_rand_reset.111727819959807050886183103792614295893472587156676265330925419236106676413708
    Line 370, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/54.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  96488761 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (712855944 [0x2a7d5188] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @  96488761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 6 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 6 failures.
  - 20.otp_ctrl_stress_all_with_rand_reset.72511746551620094792249055254286024054961092875192902278667094487232645678473
    Line 38721, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 88492626003 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 88492626003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 53.otp_ctrl_stress_all_with_rand_reset.24848812100029486193176380754247551631841789798475623550386020084776119804857
    Line 6058, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/53.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 82142376677 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 82142376677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 3 failures:

Test otp_ctrl_stress_all_with_rand_reset has 3 failures.

27.otp_ctrl_stress_all_with_rand_reset.108540745164724589332240740482320892912305998247146521608670499949735969172230
Line 4166, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 798638626997 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 798641460336 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 798642960339 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 798646627013 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 798646960347 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

85.otp_ctrl_stress_all_with_rand_reset.68226212854337992181944735623608486211411935926125554457793049082475863424362
Line 5205, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/85.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 635937926 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 635998532 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 636008633 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 636230855 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 636240956 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

... and 1 more failures.

Offending '(cio_test_en_o == *)' has 2 failures:
- Test otp_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 8.otp_ctrl_csr_mem_rw_with_rand_reset.87972611657215263741628631040359807304427493516198546314106503250411958043104
    Line 267, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  36264463 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  36264463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 19.otp_ctrl_csr_mem_rw_with_rand_reset.98730968156042420832372379485283635895541127715483211916298188500809484929521
    Line 267, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  35304817 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  35304817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 17.otp_ctrl_stress_all_with_rand_reset.86794605554269911061728038569232392275519666546664683476554012752047811177840
    Line 6397, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 824882922037 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 824882922037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.otp_ctrl_stress_all_with_rand_reset.89710841864904762984907943489106985606821651136830349340946932182263556328460
    Line 9923, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19732316738 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 19732316738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:608) [scoreboard] Check failed item.d_data == otp_a[otp_addr] (* [*] vs * [*]) mem read mismatch at TLUL addr *ebd8e*, csr_addr * has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 4.otp_ctrl_stress_all_with_rand_reset.45371703990853504709659207911679932149562643545242051919389281369341239579597
    Line 8331, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 53374958926 ps: (otp_ctrl_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed item.d_data == otp_a[otp_addr] (2810125005 [0xa77f1acd] vs 2168199885 [0x813c1acd]) mem read mismatch at TLUL addr 5ebd8e70, csr_addr 670
  UVM_INFO @ 53374958926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```