OTP_CTRL Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: d51405297e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 wake_up otp_ctrl_wake_up 1.700s 53.600us 1 1 100.00
V1 smoke otp_ctrl_smoke 33.710s 3.721ms 50 50 100.00
V1 csr_hw_reset otp_ctrl_csr_hw_reset 4.540s 1.582ms 5 5 100.00
V1 csr_rw otp_ctrl_csr_rw 1.780s 73.008us 20 20 100.00
V1 csr_bit_bash otp_ctrl_csr_bit_bash 6.950s 1.982ms 5 5 100.00
V1 csr_aliasing otp_ctrl_csr_aliasing 6.010s 346.985us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otp_ctrl_csr_mem_rw_with_rand_reset 5.950s 1.730ms 18 20 90.00
V1 regwen_csr_and_corresponding_lockable_csr otp_ctrl_csr_rw 1.780s 73.008us 20 20 100.00
otp_ctrl_csr_aliasing 6.010s 346.985us 5 5 100.00
V1 mem_walk otp_ctrl_mem_walk 1.780s 527.595us 5 5 100.00
V1 mem_partial_access otp_ctrl_mem_partial_access 1.490s 133.746us 5 5 100.00
V1 TOTAL 114 116 98.28
V2 dai_access_partition_walk otp_ctrl_partition_walk 19.820s 1.024ms 1 1 100.00
V2 init_fail otp_ctrl_init_fail 8.430s 2.015ms 300 300 100.00
V2 partition_check otp_ctrl_background_chks 43.960s 7.126ms 10 10 100.00
otp_ctrl_check_fail 1.128m 27.196ms 50 50 100.00
V2 regwen_during_otp_init otp_ctrl_regwen 19.710s 5.578ms 50 50 100.00
V2 partition_lock otp_ctrl_dai_lock 2.118m 17.286ms 50 50 100.00
V2 interface_key_check otp_ctrl_parallel_key_req 1.592m 10.179ms 50 50 100.00
V2 lc_interactions otp_ctrl_parallel_lc_req 31.480s 10.719ms 50 50 100.00
otp_ctrl_parallel_lc_esc 41.060s 18.305ms 200 200 100.00
V2 otp_dai_errors otp_ctrl_dai_errs 59.700s 24.693ms 50 50 100.00
V2 otp_macro_errors otp_ctrl_macro_errs 56.280s 18.640ms 50 50 100.00
V2 test_access otp_ctrl_test_access 1.512m 8.688ms 50 50 100.00
V2 stress_all otp_ctrl_stress_all 12.710m 131.610ms 50 50 100.00
V2 intr_test otp_ctrl_intr_test 2.030s 590.064us 50 50 100.00
V2 alert_test otp_ctrl_alert_test 2.850s 777.737us 50 50 100.00
V2 tl_d_oob_addr_access otp_ctrl_tl_errors 7.930s 2.846ms 20 20 100.00
V2 tl_d_illegal_access otp_ctrl_tl_errors 7.930s 2.846ms 20 20 100.00
V2 tl_d_outstanding_access otp_ctrl_csr_hw_reset 4.540s 1.582ms 5 5 100.00
otp_ctrl_csr_rw 1.780s 73.008us 20 20 100.00
otp_ctrl_csr_aliasing 6.010s 346.985us 5 5 100.00
otp_ctrl_same_csr_outstanding 4.810s 2.177ms 20 20 100.00
V2 tl_d_partial_access otp_ctrl_csr_hw_reset 4.540s 1.582ms 5 5 100.00
otp_ctrl_csr_rw 1.780s 73.008us 20 20 100.00
otp_ctrl_csr_aliasing 6.010s 346.985us 5 5 100.00
otp_ctrl_same_csr_outstanding 4.810s 2.177ms 20 20 100.00
V2 TOTAL 1101 1101 100.00
V2S sec_cm_additional_check otp_ctrl_sec_cm 3.409m 13.402ms 5 5 100.00
V2S tl_intg_err otp_ctrl_sec_cm 3.409m 13.402ms 5 5 100.00
otp_ctrl_tl_intg_err 34.670s 20.087ms 20 20 100.00
V2S prim_count_check otp_ctrl_sec_cm 3.409m 13.402ms 5 5 100.00
V2S prim_fsm_check otp_ctrl_sec_cm 3.409m 13.402ms 5 5 100.00
V2S sec_cm_bus_integrity otp_ctrl_tl_intg_err 34.670s 20.087ms 20 20 100.00
V2S sec_cm_secret_mem_scramble otp_ctrl_smoke 33.710s 3.721ms 50 50 100.00
V2S sec_cm_part_mem_digest otp_ctrl_smoke 33.710s 3.721ms 50 50 100.00
V2S sec_cm_dai_fsm_sparse otp_ctrl_sec_cm 3.409m 13.402ms 5 5 100.00
V2S sec_cm_kdi_fsm_sparse otp_ctrl_sec_cm 3.409m 13.402ms 5 5 100.00
V2S sec_cm_lci_fsm_sparse otp_ctrl_sec_cm 3.409m 13.402ms 5 5 100.00
V2S sec_cm_part_fsm_sparse otp_ctrl_sec_cm 3.409m 13.402ms 5 5 100.00
V2S sec_cm_scrmbl_fsm_sparse otp_ctrl_sec_cm 3.409m 13.402ms 5 5 100.00
V2S sec_cm_timer_fsm_sparse otp_ctrl_sec_cm 3.409m 13.402ms 5 5 100.00
V2S sec_cm_dai_ctr_redun otp_ctrl_sec_cm 3.409m 13.402ms 5 5 100.00
V2S sec_cm_kdi_seed_ctr_redun otp_ctrl_sec_cm 3.409m 13.402ms 5 5 100.00
V2S sec_cm_kdi_entropy_ctr_redun otp_ctrl_sec_cm 3.409m 13.402ms 5 5 100.00
V2S sec_cm_lci_ctr_redun otp_ctrl_sec_cm 3.409m 13.402ms 5 5 100.00
V2S sec_cm_part_ctr_redun otp_ctrl_sec_cm 3.409m 13.402ms 5 5 100.00
V2S sec_cm_scrmbl_ctr_redun otp_ctrl_sec_cm 3.409m 13.402ms 5 5 100.00
V2S sec_cm_timer_integ_ctr_redun otp_ctrl_sec_cm 3.409m 13.402ms 5 5 100.00
V2S sec_cm_timer_cnsty_ctr_redun otp_ctrl_sec_cm 3.409m 13.402ms 5 5 100.00
V2S sec_cm_timer_lfsr_redun otp_ctrl_sec_cm 3.409m 13.402ms 5 5 100.00
V2S sec_cm_dai_fsm_local_esc otp_ctrl_parallel_lc_esc 41.060s 18.305ms 200 200 100.00
otp_ctrl_sec_cm 3.409m 13.402ms 5 5 100.00
V2S sec_cm_lci_fsm_local_esc otp_ctrl_parallel_lc_esc 41.060s 18.305ms 200 200 100.00
V2S sec_cm_kdi_fsm_local_esc otp_ctrl_parallel_lc_esc 41.060s 18.305ms 200 200 100.00
V2S sec_cm_part_fsm_local_esc otp_ctrl_parallel_lc_esc 41.060s 18.305ms 200 200 100.00
otp_ctrl_macro_errs 56.280s 18.640ms 50 50 100.00
V2S sec_cm_scrmbl_fsm_local_esc otp_ctrl_parallel_lc_esc 41.060s 18.305ms 200 200 100.00
V2S sec_cm_timer_fsm_local_esc otp_ctrl_parallel_lc_esc 41.060s 18.305ms 200 200 100.00
otp_ctrl_sec_cm 3.409m 13.402ms 5 5 100.00
V2S sec_cm_dai_fsm_global_esc otp_ctrl_parallel_lc_esc 41.060s 18.305ms 200 200 100.00
otp_ctrl_sec_cm 3.409m 13.402ms 5 5 100.00
V2S sec_cm_lci_fsm_global_esc otp_ctrl_parallel_lc_esc 41.060s 18.305ms 200 200 100.00
V2S sec_cm_kdi_fsm_global_esc otp_ctrl_parallel_lc_esc 41.060s 18.305ms 200 200 100.00
V2S sec_cm_part_fsm_global_esc otp_ctrl_parallel_lc_esc 41.060s 18.305ms 200 200 100.00
otp_ctrl_macro_errs 56.280s 18.640ms 50 50 100.00
V2S sec_cm_scrmbl_fsm_global_esc otp_ctrl_parallel_lc_esc 41.060s 18.305ms 200 200 100.00
V2S sec_cm_timer_fsm_global_esc otp_ctrl_parallel_lc_esc 41.060s 18.305ms 200 200 100.00
otp_ctrl_sec_cm 3.409m 13.402ms 5 5 100.00
V2S sec_cm_part_data_reg_integrity otp_ctrl_init_fail 8.430s 2.015ms 300 300 100.00
V2S sec_cm_part_data_reg_bkgn_chk otp_ctrl_check_fail 1.128m 27.196ms 50 50 100.00
V2S sec_cm_part_mem_regren otp_ctrl_dai_lock 2.118m 17.286ms 50 50 100.00
V2S sec_cm_part_mem_sw_unreadable otp_ctrl_dai_lock 2.118m 17.286ms 50 50 100.00
V2S sec_cm_part_mem_sw_unwritable otp_ctrl_dai_lock 2.118m 17.286ms 50 50 100.00
V2S sec_cm_lc_part_mem_sw_noaccess otp_ctrl_dai_lock 2.118m 17.286ms 50 50 100.00
V2S sec_cm_access_ctrl_mubi otp_ctrl_dai_lock 2.118m 17.286ms 50 50 100.00
V2S sec_cm_token_valid_ctrl_mubi otp_ctrl_smoke 33.710s 3.721ms 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi otp_ctrl_dai_lock 2.118m 17.286ms 50 50 100.00
V2S sec_cm_test_bus_lc_gated otp_ctrl_smoke 33.710s 3.721ms 50 50 100.00
V2S sec_cm_test_tl_lc_gate_fsm_sparse otp_ctrl_sec_cm 3.409m 13.402ms 5 5 100.00
V2S sec_cm_direct_access_config_regwen otp_ctrl_regwen 19.710s 5.578ms 50 50 100.00
V2S sec_cm_check_trigger_config_regwen otp_ctrl_smoke 33.710s 3.721ms 50 50 100.00
V2S sec_cm_check_config_regwen otp_ctrl_smoke 33.710s 3.721ms 50 50 100.00
V2S sec_cm_macro_mem_integrity otp_ctrl_macro_errs 56.280s 18.640ms 50 50 100.00
V2S TOTAL 25 25 100.00
V3 otp_ctrl_low_freq_read otp_ctrl_low_freq_read 10.700s 3.051ms 1 1 100.00
V3 stress_all_with_rand_reset otp_ctrl_stress_all_with_rand_reset 1.414h 2.203s 81 100 81.00
V3 TOTAL 82 101 81.19
TOTAL 1322 1343 98.44

Testplan Progress

Items Total Written Passing Progress
V1 9 9 8 88.89
V2 17 17 17 100.00
V2S 2 2 2 100.00
V3 2 2 1 50.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.92 93.76 96.18 95.67 92.12 97.05 96.34 93.35

Failure Buckets

Past Results