OTP_CTRL Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: `c04cc5d074`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.830s	99.849us	1	1	100.00
V1	smoke	otp_ctrl_smoke	22.980s	4.255ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.570s	112.197us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.580s	655.480us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	13.220s	6.885ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	7.650s	3.010ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	3.980s	213.790us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.580s	655.480us	20	20	100.00
		otp_ctrl_csr_aliasing	7.650s	3.010ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.670s	548.508us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.990s	533.012us	5	5	100.00
V1		TOTAL			115	116	99.14
V2	dai_access_partition_walk	otp_ctrl_partition_walk	19.040s	794.710us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.550s	2.950ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	46.360s	2.825ms	10	10	100.00
		otp_ctrl_check_fail	3.691m	31.405ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	17.300s	5.409ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.811m	11.600ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	46.610s	3.634ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	36.620s	12.303ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	36.250s	13.523ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	49.810s	5.836ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.262m	9.863ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	54.050s	4.871ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	5.334m	188.498ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.200s	570.794us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.040s	1.006ms	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.480s	688.808us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.480s	688.808us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.570s	112.197us	5	5	100.00
		otp_ctrl_csr_rw	2.580s	655.480us	20	20	100.00
		otp_ctrl_csr_aliasing	7.650s	3.010ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.700s	231.913us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.570s	112.197us	5	5	100.00
		otp_ctrl_csr_rw	2.580s	655.480us	20	20	100.00
		otp_ctrl_csr_aliasing	7.650s	3.010ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.700s	231.913us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	6.069m	165.624ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	6.069m	165.624ms	5	5	100.00
		otp_ctrl_tl_intg_err	34.050s	20.133ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	6.069m	165.624ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	6.069m	165.624ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	34.050s	20.133ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	22.980s	4.255ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	22.980s	4.255ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	6.069m	165.624ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	6.069m	165.624ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	6.069m	165.624ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	6.069m	165.624ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	6.069m	165.624ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	6.069m	165.624ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	6.069m	165.624ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	6.069m	165.624ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	6.069m	165.624ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	6.069m	165.624ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	6.069m	165.624ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	6.069m	165.624ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	6.069m	165.624ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	6.069m	165.624ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	6.069m	165.624ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.250s	13.523ms	200	200	100.00
		otp_ctrl_sec_cm	6.069m	165.624ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.250s	13.523ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.250s	13.523ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.250s	13.523ms	200	200	100.00
		otp_ctrl_macro_errs	1.262m	9.863ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.250s	13.523ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.250s	13.523ms	200	200	100.00
		otp_ctrl_sec_cm	6.069m	165.624ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.250s	13.523ms	200	200	100.00
		otp_ctrl_sec_cm	6.069m	165.624ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.250s	13.523ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.250s	13.523ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.250s	13.523ms	200	200	100.00
		otp_ctrl_macro_errs	1.262m	9.863ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.250s	13.523ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.250s	13.523ms	200	200	100.00
		otp_ctrl_sec_cm	6.069m	165.624ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.550s	2.950ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	3.691m	31.405ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.811m	11.600ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.811m	11.600ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.811m	11.600ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.811m	11.600ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.811m	11.600ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	22.980s	4.255ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.811m	11.600ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	22.980s	4.255ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	6.069m	165.624ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	17.300s	5.409ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	22.980s	4.255ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	22.980s	4.255ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.262m	9.863ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	13.200s	3.069ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.204h	1.134s	74	100	74.00
V3		TOTAL			75	101	74.26
		TOTAL			1316	1343	97.99

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.08	93.81	96.75	96.20	91.89	97.24	96.34	93.35

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 13 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 13 failures.
  - 0.otp_ctrl_stress_all_with_rand_reset.30240396037190309166967900719570702148934471846452495520420635525231835991883
    Line 61339, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 104978807416 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 104978807416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.otp_ctrl_stress_all_with_rand_reset.47197783224949023604502427445644835127350292758155695420363115119093065988459
    Line 55717, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14986524091 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 14986524091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 10 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 10 failures.
  - 8.otp_ctrl_stress_all_with_rand_reset.4085950528671267285502803755774465983933968678012545502053949665369138625999
    Line 344, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  78774302 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1399182948 [0x5365d664] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @  78774302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.otp_ctrl_stress_all_with_rand_reset.79779934568827062324579338450162686102739658994719247524948180347431296522792
    Line 332, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 127791763 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1579663048 [0x5e27bec8] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 127791763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
Offending '(cio_test_en_o == *)' has 2 failures:
- Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 19.otp_ctrl_csr_mem_rw_with_rand_reset.37730001355079459285807704921023627542785309184410437394829478827837962628218
    Line 267, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  52780883 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  52780883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 59.otp_ctrl_stress_all_with_rand_reset.68216747415102439278086146873493100473953419786852549782784030135536373295596
    Line 6028, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/59.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 18957198635 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 18957198635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:749) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 33.otp_ctrl_stress_all_with_rand_reset.99992653977537148916930036609097424606128080519608369483396103514965492497689
    Line 67236, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 83393946878 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 83393946878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 35.otp_ctrl_stress_all_with_rand_reset.107077572222374840335706642371798908757262382780461503245929905046191536582071
    Line 42336, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1059329968084 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 604 [0x25c]) dai addr 25c rdata0 readout mismatch
  UVM_INFO @ 1059329968084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

OTP_CTRL Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: c04cc5d074

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c04cc5d074`