OTP_CTRL Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: `a04e34f557`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	2.590s	797.034us	1	1	100.00
V1	smoke	otp_ctrl_smoke	33.110s	5.936ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.490s	100.905us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.010s	554.852us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	9.460s	794.428us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	7.640s	2.596ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.410s	107.844us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.010s	554.852us	20	20	100.00
		otp_ctrl_csr_aliasing	7.640s	2.596ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.590s	546.571us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.610s	552.381us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	19.610s	1.229ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	9.070s	3.103ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	44.310s	2.438ms	10	10	100.00
		otp_ctrl_check_fail	48.820s	4.383ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	18.500s	5.539ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	57.050s	22.437ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.127m	30.184ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	35.120s	9.856ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	31.590s	15.382ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	39.060s	1.572ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.092m	8.258ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.638m	12.737ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	9.044m	49.743ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.230s	581.404us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.520s	548.161us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	10.360s	2.632ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	10.360s	2.632ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.490s	100.905us	5	5	100.00
		otp_ctrl_csr_rw	2.010s	554.852us	20	20	100.00
		otp_ctrl_csr_aliasing	7.640s	2.596ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.310s	1.388ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.490s	100.905us	5	5	100.00
		otp_ctrl_csr_rw	2.010s	554.852us	20	20	100.00
		otp_ctrl_csr_aliasing	7.640s	2.596ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.310s	1.388ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.369m	42.592ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.369m	42.592ms	5	5	100.00
		otp_ctrl_tl_intg_err	25.640s	19.916ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.369m	42.592ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.369m	42.592ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	25.640s	19.916ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	33.110s	5.936ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	33.110s	5.936ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.369m	42.592ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.369m	42.592ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.369m	42.592ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.369m	42.592ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.369m	42.592ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.369m	42.592ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.369m	42.592ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.369m	42.592ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.369m	42.592ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.369m	42.592ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.369m	42.592ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.369m	42.592ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.369m	42.592ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.369m	42.592ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.369m	42.592ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	31.590s	15.382ms	200	200	100.00
		otp_ctrl_sec_cm	3.369m	42.592ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	31.590s	15.382ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	31.590s	15.382ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	31.590s	15.382ms	200	200	100.00
		otp_ctrl_macro_errs	1.092m	8.258ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	31.590s	15.382ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	31.590s	15.382ms	200	200	100.00
		otp_ctrl_sec_cm	3.369m	42.592ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	31.590s	15.382ms	200	200	100.00
		otp_ctrl_sec_cm	3.369m	42.592ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	31.590s	15.382ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	31.590s	15.382ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	31.590s	15.382ms	200	200	100.00
		otp_ctrl_macro_errs	1.092m	8.258ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	31.590s	15.382ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	31.590s	15.382ms	200	200	100.00
		otp_ctrl_sec_cm	3.369m	42.592ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	9.070s	3.103ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	48.820s	4.383ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	57.050s	22.437ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	57.050s	22.437ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	57.050s	22.437ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	57.050s	22.437ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	57.050s	22.437ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	33.110s	5.936ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	57.050s	22.437ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	33.110s	5.936ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.369m	42.592ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	18.500s	5.539ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	33.110s	5.936ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	33.110s	5.936ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.092m	8.258ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	10.260s	5.968ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.076h	230.581ms	83	100	83.00
V3		TOTAL			84	101	83.17
		TOTAL			1326	1343	98.73

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.99	93.76	96.65	96.04	91.65	97.19	96.34	93.28

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 7 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 7 failures.
  - 3.otp_ctrl_stress_all_with_rand_reset.54609504442852701974924984842983973604725412855479506273942180424355471676282
    Line 61819, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 22188393693 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3508982106 [0xd126d15a] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 22188393693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.otp_ctrl_stress_all_with_rand_reset.62468960520953848236587471138512292104513030789297923816389499047775759849511
    Line 15099, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18720808537 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2055531231 [0x7a84eadf] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 18720808537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 6 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 6 failures.
  - 1.otp_ctrl_stress_all_with_rand_reset.3768077624030019801455634517219021669532083141888656915835820548834135319251
    Line 16874, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 104258954558 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 104258954558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.otp_ctrl_stress_all_with_rand_reset.20215100201147760321128548135750993813322912618252804057048979511464309621524
    Line 40133, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 681964710369 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 681964710369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Offending '(cio_test_en_o == *)' has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 29.otp_ctrl_stress_all_with_rand_reset.28274889750700267395751335819573950102484833848746319869376298396769253570871
    Line 73147, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 238092819058 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 238092819058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 89.otp_ctrl_stress_all_with_rand_reset.64670921111649460711642101278932353956406247784022507167239544005338040142373
    Line 54112, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/89.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 924456310626 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 924456310626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

31.otp_ctrl_stress_all_with_rand_reset.3768246720245324508976674311858004039475283895539195785872969211908623348952
Line 52016, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 260939791054 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 260939957721 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 260942457726 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 260944124396 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 260948624405 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (cip_base_vseq.sv:825) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 69.otp_ctrl_stress_all_with_rand_reset.59947021754143200800001010401946275894784047356261332247007871870445159039071
    Line 17405, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/69.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20612327419 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 20612327419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```