OTP_CTRL Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: aad711e1bc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.770s	102.581us	1	1	100.00
V1	smoke	otp_ctrl_smoke	21.150s	7.598ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.500s	196.604us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.400s	627.928us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	9.280s	471.484us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.960s	394.896us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.300s	118.155us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.400s	627.928us	20	20	100.00
		otp_ctrl_csr_aliasing	6.960s	394.896us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.660s	514.621us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.470s	504.015us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	19.400s	1.190ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.320s	2.510ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	33.930s	7.272ms	10	10	100.00
		otp_ctrl_check_fail	1.474m	23.305ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	12.650s	1.319ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	5.744m	46.983ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.209m	21.992ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	31.500s	3.684ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	40.260s	13.551ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	46.180s	17.304ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.200m	5.482ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.448m	19.232ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	6.335m	58.021ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.130s	600.005us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.050s	218.209us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	6.690s	611.177us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	6.690s	611.177us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.500s	196.604us	5	5	100.00
		otp_ctrl_csr_rw	2.400s	627.928us	20	20	100.00
		otp_ctrl_csr_aliasing	6.960s	394.896us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.590s	133.353us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.500s	196.604us	5	5	100.00
		otp_ctrl_csr_rw	2.400s	627.928us	20	20	100.00
		otp_ctrl_csr_aliasing	6.960s	394.896us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.590s	133.353us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.959m	39.745ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.959m	39.745ms	5	5	100.00
		otp_ctrl_tl_intg_err	30.130s	20.034ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.959m	39.745ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.959m	39.745ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	30.130s	20.034ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	21.150s	7.598ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	21.150s	7.598ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.959m	39.745ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.959m	39.745ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.959m	39.745ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.959m	39.745ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.959m	39.745ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.959m	39.745ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.959m	39.745ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.959m	39.745ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.959m	39.745ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.959m	39.745ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.959m	39.745ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.959m	39.745ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.959m	39.745ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.959m	39.745ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.959m	39.745ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	40.260s	13.551ms	200	200	100.00
		otp_ctrl_sec_cm	3.959m	39.745ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	40.260s	13.551ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	40.260s	13.551ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	40.260s	13.551ms	200	200	100.00
		otp_ctrl_macro_errs	1.200m	5.482ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	40.260s	13.551ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	40.260s	13.551ms	200	200	100.00
		otp_ctrl_sec_cm	3.959m	39.745ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	40.260s	13.551ms	200	200	100.00
		otp_ctrl_sec_cm	3.959m	39.745ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	40.260s	13.551ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	40.260s	13.551ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	40.260s	13.551ms	200	200	100.00
		otp_ctrl_macro_errs	1.200m	5.482ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	40.260s	13.551ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	40.260s	13.551ms	200	200	100.00
		otp_ctrl_sec_cm	3.959m	39.745ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.320s	2.510ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.474m	23.305ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	5.744m	46.983ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	5.744m	46.983ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	5.744m	46.983ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	5.744m	46.983ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	5.744m	46.983ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	21.150s	7.598ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	5.744m	46.983ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	21.150s	7.598ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.959m	39.745ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	12.650s	1.319ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	21.150s	7.598ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	21.150s	7.598ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.200m	5.482ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	15.030s	5.933ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.074h	1.584s	84	100	84.00
V3		TOTAL			85	101	84.16
		TOTAL			1327	1343	98.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.94	93.76	96.23	95.69	92.12	97.05	96.34	93.35

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 7 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 7 failures.

    • 1.otp_ctrl_stress_all_with_rand_reset.109201765176890778549128194900702490921169380161318449869146769564797967323169
      Line 24020, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 977612942936 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4225211431 [0xfbd79c27] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 977612942936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.otp_ctrl_stress_all_with_rand_reset.100446671642208617082468382375300414426732702200646522856773496179693425702978
      Line 335, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 598218012 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (173685921 [0xa5a3ca1] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 598218012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 7 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 7 failures.

    • 12.otp_ctrl_stress_all_with_rand_reset.60025982698577074303918472290759557007670720442615696285104193765904270888455
      Line 8471, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1429571398 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 1429571398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 16.otp_ctrl_stress_all_with_rand_reset.49478381680883748798329098267113323694879834014087293295505009836078836132012
      Line 6260, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 45229401198 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 45229401198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• Offending '(cio_test_en_o == *)' has 2 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

    • 28.otp_ctrl_stress_all_with_rand_reset.54447189286453690169556232456875053497630667216350134391796619236012966562902
      Line 26505, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 19781467204 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 19781467204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 59.otp_ctrl_stress_all_with_rand_reset.80168887406143013201820256866855766621801139029476961037048623107572461278369
      Line 56143, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/59.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 83681509124 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 83681509124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.07.16_09.41.52
• 2024.07.15_09.30.41
• 2024.07.14_08.46.35
• 2024.07.13_08.25.38
• 2024.07.12_09.12.36
• 2024.07.11_10.37.44