OTP_CTRL Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: `8b2da8db5e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.780s	55.075us	1	1	100.00
V1	smoke	otp_ctrl_smoke	14.320s	4.734ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.470s	184.869us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.250s	553.540us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	8.670s	685.124us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.480s	186.411us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	3.790s	1.068ms	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.250s	553.540us	20	20	100.00
		otp_ctrl_csr_aliasing	6.480s	186.411us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.660s	505.964us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.720s	517.218us	5	5	100.00
V1		TOTAL			114	116	98.28
V2	dai_access_partition_walk	otp_ctrl_partition_walk	18.180s	621.537us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.170s	2.520ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	54.060s	23.039ms	10	10	100.00
		otp_ctrl_check_fail	43.430s	11.801ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	14.550s	4.343ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	46.010s	17.559ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	48.480s	6.179ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	28.610s	8.255ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	34.760s	13.967ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.262m	23.339ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.059m	29.108ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.909m	20.874ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	7.138m	30.466ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.200s	611.868us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	4.630s	461.388us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	6.880s	2.305ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	6.880s	2.305ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.470s	184.869us	5	5	100.00
		otp_ctrl_csr_rw	2.250s	553.540us	20	20	100.00
		otp_ctrl_csr_aliasing	6.480s	186.411us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.130s	1.173ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.470s	184.869us	5	5	100.00
		otp_ctrl_csr_rw	2.250s	553.540us	20	20	100.00
		otp_ctrl_csr_aliasing	6.480s	186.411us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.130s	1.173ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.133m	173.357ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.133m	173.357ms	5	5	100.00
		otp_ctrl_tl_intg_err	21.570s	5.254ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.133m	173.357ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.133m	173.357ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	21.570s	5.254ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	14.320s	4.734ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	14.320s	4.734ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.133m	173.357ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.133m	173.357ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.133m	173.357ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.133m	173.357ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.133m	173.357ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.133m	173.357ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.133m	173.357ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.133m	173.357ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.133m	173.357ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.133m	173.357ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.133m	173.357ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.133m	173.357ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.133m	173.357ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.133m	173.357ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.133m	173.357ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.760s	13.967ms	200	200	100.00
		otp_ctrl_sec_cm	4.133m	173.357ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.760s	13.967ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.760s	13.967ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.760s	13.967ms	200	200	100.00
		otp_ctrl_macro_errs	1.059m	29.108ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.760s	13.967ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.760s	13.967ms	200	200	100.00
		otp_ctrl_sec_cm	4.133m	173.357ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.760s	13.967ms	200	200	100.00
		otp_ctrl_sec_cm	4.133m	173.357ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.760s	13.967ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.760s	13.967ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.760s	13.967ms	200	200	100.00
		otp_ctrl_macro_errs	1.059m	29.108ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.760s	13.967ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.760s	13.967ms	200	200	100.00
		otp_ctrl_sec_cm	4.133m	173.357ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.170s	2.520ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	43.430s	11.801ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	46.010s	17.559ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	46.010s	17.559ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	46.010s	17.559ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	46.010s	17.559ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	46.010s	17.559ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	14.320s	4.734ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	46.010s	17.559ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	14.320s	4.734ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.133m	173.357ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	14.550s	4.343ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	14.320s	4.734ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	14.320s	4.734ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.059m	29.108ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	14.610s	6.301ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.237h	1.764s	75	100	75.00
V3		TOTAL			76	101	75.25
		TOTAL			1316	1343	97.99

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.72	93.76	96.15	95.52	91.17	96.81	96.34	93.28

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 8 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 8 failures.
  - 2.otp_ctrl_stress_all_with_rand_reset.84065360898817396619909933314763773209591158111107125855064798104703440520217
    Line 667, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 331980104 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3136802964 [0xbaf7d094] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 331980104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.otp_ctrl_stress_all_with_rand_reset.95763547463335420527334991243242431698432523675478258233514059160190696559288
    Line 11169, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14773440228 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1796773746 [0x6b189772] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_1
  UVM_INFO @ 14773440228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 8 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 8 failures.
  - 11.otp_ctrl_stress_all_with_rand_reset.97708290819033803915457858129120394024193193515332127340027190953566977739628
    Line 57528, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 389345926029 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 389345926029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.otp_ctrl_stress_all_with_rand_reset.73993646602956315938914961670514360898224961000272774510637283216887009927670
    Line 19670, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 188698946913 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 188698946913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
Offending '(cio_test_en_o == *)' has 3 failures:
- Test otp_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 9.otp_ctrl_csr_mem_rw_with_rand_reset.14993806527720002947036359799639190533541682434759380140510395914349896812429
    Line 267, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  48345016 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  48345016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 12.otp_ctrl_csr_mem_rw_with_rand_reset.51364991107530793683296392981213696865166778049794909475082863955702888444130
    Line 267, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  27329466 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  27329466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 29.otp_ctrl_stress_all_with_rand_reset.35398931907206399614815205174212379947894201099023420666302539635031721017480
    Line 37912, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 27269414188 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 27269414188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 2 failures:

Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

28.otp_ctrl_stress_all_with_rand_reset.10823025604062326190758227930546817664123937127964946443372644729900135873860
Line 39075, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 28879023253 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 28879367014 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 28879377431 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 28879835779 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 28879846196 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

70.otp_ctrl_stress_all_with_rand_reset.5355024377303019672227109454229401971605576437954231412137276307043948856258
Line 111257, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/70.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 402645906993 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 402647406996 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 402648240331 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 402654407010 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 402655407012 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (cip_base_vseq.sv:839) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 50.otp_ctrl_stress_all_with_rand_reset.42266423900802420044977693013285337702641677543933233521502510131045594478171
    Line 123238, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/50.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 144674789218 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 144674789218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 86.otp_ctrl_stress_all_with_rand_reset.32748361291950645792479733702319769278160983628347467225042329705011081282439
    Line 85014, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/86.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 931099229075 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 931099229075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 30.otp_ctrl_stress_all_with_rand_reset.60517934059513250933719337172493571628887992662916300864074243075634628618574
    Line 3397, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 958253454490 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 2136759108 [0x7f5c5b44]) dai addr 728 rdata0 readout mismatch
  UVM_INFO @ 958253454490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 54.otp_ctrl_stress_all_with_rand_reset.54947613914793127020260324621974158856659039542982535287153421426766046570978
    Line 11172, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/54.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26619813178 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 26619813178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=*) == * has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 60.otp_ctrl_stress_all_with_rand_reset.8230831352701857224136094950924271241912116467802634257835200139585587088795
    Line 43944, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/60.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 324744893006 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=0x1121f010) == 0x0
  UVM_INFO @ 324744893006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *cc rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 80.otp_ctrl_stress_all_with_rand_reset.115685557924683125197745118258596221317555458743802898092436294572243509497461
    Line 5020, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/80.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13625242122 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1736 [0x6c8]) dai addr 6cc rdata0 readout mismatch
  UVM_INFO @ 13625242122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```