OTP_CTRL Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: `974aaab627`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.850s	196.888us	1	1	100.00
V1	smoke	otp_ctrl_smoke	20.850s	8.069ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.680s	388.530us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.910s	602.940us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	9.150s	522.849us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	7.670s	2.592ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.210s	141.465us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.910s	602.940us	20	20	100.00
		otp_ctrl_csr_aliasing	7.670s	2.592ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.810s	496.630us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.560s	507.247us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	18.680s	313.964us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.010s	2.603ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	41.270s	4.451ms	10	10	100.00
		otp_ctrl_check_fail	45.050s	7.214ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	15.650s	5.000ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	41.490s	4.620ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.153m	2.875ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	30.340s	908.242us	50	50	100.00
		otp_ctrl_parallel_lc_esc	53.350s	15.914ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	52.840s	5.437ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.103m	24.490ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	57.580s	22.821ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	10.788m	110.450ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.100s	509.039us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	4.580s	430.329us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	10.960s	2.996ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	10.960s	2.996ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.680s	388.530us	5	5	100.00
		otp_ctrl_csr_rw	1.910s	602.940us	20	20	100.00
		otp_ctrl_csr_aliasing	7.670s	2.592ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.790s	484.967us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.680s	388.530us	5	5	100.00
		otp_ctrl_csr_rw	1.910s	602.940us	20	20	100.00
		otp_ctrl_csr_aliasing	7.670s	2.592ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.790s	484.967us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	6.588m	165.516ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	6.588m	165.516ms	5	5	100.00
		otp_ctrl_tl_intg_err	29.980s	20.035ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	6.588m	165.516ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	6.588m	165.516ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	29.980s	20.035ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	20.850s	8.069ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	20.850s	8.069ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	6.588m	165.516ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	6.588m	165.516ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	6.588m	165.516ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	6.588m	165.516ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	6.588m	165.516ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	6.588m	165.516ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	6.588m	165.516ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	6.588m	165.516ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	6.588m	165.516ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	6.588m	165.516ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	6.588m	165.516ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	6.588m	165.516ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	6.588m	165.516ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	6.588m	165.516ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	6.588m	165.516ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	53.350s	15.914ms	200	200	100.00
		otp_ctrl_sec_cm	6.588m	165.516ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	53.350s	15.914ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	53.350s	15.914ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	53.350s	15.914ms	200	200	100.00
		otp_ctrl_macro_errs	1.103m	24.490ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	53.350s	15.914ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	53.350s	15.914ms	200	200	100.00
		otp_ctrl_sec_cm	6.588m	165.516ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	53.350s	15.914ms	200	200	100.00
		otp_ctrl_sec_cm	6.588m	165.516ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	53.350s	15.914ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	53.350s	15.914ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	53.350s	15.914ms	200	200	100.00
		otp_ctrl_macro_errs	1.103m	24.490ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	53.350s	15.914ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	53.350s	15.914ms	200	200	100.00
		otp_ctrl_sec_cm	6.588m	165.516ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.010s	2.603ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	45.050s	7.214ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	41.490s	4.620ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	41.490s	4.620ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	41.490s	4.620ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	41.490s	4.620ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	41.490s	4.620ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	20.850s	8.069ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	41.490s	4.620ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	20.850s	8.069ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	6.588m	165.516ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	15.650s	5.000ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	20.850s	8.069ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	20.850s	8.069ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.103m	24.490ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	11.810s	3.050ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.042h	1.290s	75	100	75.00
V3		TOTAL			76	101	75.25
		TOTAL			1318	1343	98.14

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.82	93.83	96.30	95.63	91.17	97.10	96.34	93.35

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 11 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 11 failures.
  - 8.otp_ctrl_stress_all_with_rand_reset.83550510475995532487481779706008820969185370136317793943553980689726703815816
    Line 68972, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14712781691 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 14712781691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.otp_ctrl_stress_all_with_rand_reset.862604994784490706074163089282142628893044969017648523683573090937118469085
    Line 15813, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 422793691497 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 422793691497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 7 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 7 failures.
  - 29.otp_ctrl_stress_all_with_rand_reset.103320268937574909201440686468281422376191431880846849061938298411082330188643
    Line 79037, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 146554926962 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1143883504 [0x442e46f0] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 146554926962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 30.otp_ctrl_stress_all_with_rand_reset.58106248663684064561385742406496624104013569502712541118307817765504992684277
    Line 6072, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 31667221451 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2674497034 [0x9f69960a] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 31667221451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_ERROR (cip_base_vseq.sv:839) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 81.otp_ctrl_stress_all_with_rand_reset.53801185084310488690620067285334660967043184564051013966502364039036337752219
    Line 2569, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/81.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 288828891 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 288828891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 99.otp_ctrl_stress_all_with_rand_reset.85733863152530545449230885097145298465665820431637484535537521779844277934939
    Line 193290, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/99.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 487312388802 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 487312388802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 17.otp_ctrl_stress_all_with_rand_reset.34526295235501758860169131631552138074008309178086385375752190534949606342050
    Line 67201, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 60812609267 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 3967950184 [0xec821d68]) dai addr 708 rdata0 readout mismatch
  UVM_INFO @ 60812609267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(cio_test_en_o == *)' has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 26.otp_ctrl_stress_all_with_rand_reset.11511593590407616296204281077307948669877684954960909434892403249046365958032
    Line 4128, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 3964086359 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 3964086359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.dai_idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=784) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 32.otp_ctrl_stress_all_with_rand_reset.93382756210343504723725633735250993391356037876961366115836294656877193771825
    Line 50699, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 75058062717 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.dai_idle (addr=0xb2a0b010, Comparison=CompareOpEq, exp_data=0x1, call_count=784)
  UVM_INFO @ 75058062717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.dai_idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=420) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 91.otp_ctrl_stress_all_with_rand_reset.60443762950098500692289497380520578694750710565349223043395678264867910455707
    Line 31332, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/91.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 159518446674 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.dai_idle (addr=0x66108010, Comparison=CompareOpEq, exp_data=0x1, call_count=420)
  UVM_INFO @ 159518446674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 97.otp_ctrl_stress_all_with_rand_reset.27424650996499577255243621865873986323096292461077778738226117587662926402456
    Line 6587, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/97.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6053885456 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 6053885456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

OTP_CTRL Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: 974aaab627

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `974aaab627`