OTP_CTRL Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.700s	95.111us	1	1	100.00
V1	smoke	otp_ctrl_smoke	13.930s	1.503ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.300s	98.565us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.290s	549.911us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	10.520s	515.122us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	7.210s	2.539ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	5.740s	1.617ms	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.290s	549.911us	20	20	100.00
		otp_ctrl_csr_aliasing	7.210s	2.539ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.450s	512.250us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.410s	100.796us	5	5	100.00
V1		TOTAL			115	116	99.14
V2	dai_access_partition_walk	otp_ctrl_partition_walk	30.560s	9.970ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.240s	3.028ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	56.120s	8.261ms	10	10	100.00
		otp_ctrl_check_fail	50.740s	26.319ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	13.250s	1.330ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.608m	9.611ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.401m	13.420ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	40.320s	13.910ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	34.400s	11.523ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	52.760s	2.973ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.311m	26.231ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.228m	28.847ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	11.475m	51.445ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	1.780s	534.877us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.930s	198.909us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	11.220s	2.706ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	11.220s	2.706ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.300s	98.565us	5	5	100.00
		otp_ctrl_csr_rw	2.290s	549.911us	20	20	100.00
		otp_ctrl_csr_aliasing	7.210s	2.539ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.070s	1.964ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.300s	98.565us	5	5	100.00
		otp_ctrl_csr_rw	2.290s	549.911us	20	20	100.00
		otp_ctrl_csr_aliasing	7.210s	2.539ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.070s	1.964ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.312m	154.718ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.312m	154.718ms	5	5	100.00
		otp_ctrl_tl_intg_err	40.500s	20.026ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.312m	154.718ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.312m	154.718ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	40.500s	20.026ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	13.930s	1.503ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	13.930s	1.503ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.312m	154.718ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.312m	154.718ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.312m	154.718ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.312m	154.718ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.312m	154.718ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.312m	154.718ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.312m	154.718ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.312m	154.718ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.312m	154.718ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.312m	154.718ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.312m	154.718ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.312m	154.718ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.312m	154.718ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.312m	154.718ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.312m	154.718ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.400s	11.523ms	200	200	100.00
		otp_ctrl_sec_cm	4.312m	154.718ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.400s	11.523ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.400s	11.523ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.400s	11.523ms	200	200	100.00
		otp_ctrl_macro_errs	1.311m	26.231ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.400s	11.523ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.400s	11.523ms	200	200	100.00
		otp_ctrl_sec_cm	4.312m	154.718ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.400s	11.523ms	200	200	100.00
		otp_ctrl_sec_cm	4.312m	154.718ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.400s	11.523ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.400s	11.523ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.400s	11.523ms	200	200	100.00
		otp_ctrl_macro_errs	1.311m	26.231ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.400s	11.523ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.400s	11.523ms	200	200	100.00
		otp_ctrl_sec_cm	4.312m	154.718ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.240s	3.028ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	50.740s	26.319ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.608m	9.611ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.608m	9.611ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.608m	9.611ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.608m	9.611ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.608m	9.611ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	13.930s	1.503ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.608m	9.611ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	13.930s	1.503ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.312m	154.718ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	13.250s	1.330ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	13.930s	1.503ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	13.930s	1.503ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.311m	26.231ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	15.440s	7.557ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.147h	1.669s	81	100	81.00
V3		TOTAL			82	101	81.19
		TOTAL			1323	1343	98.51

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.89	93.81	96.18	95.61	91.89	97.10	96.34	93.28

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 9 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 9 failures.
  - 9.otp_ctrl_stress_all_with_rand_reset.100428530896835291331862793108515797203207523574726616752220925462533442408945
    Line 6673, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 625952996847 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 625952996847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.otp_ctrl_stress_all_with_rand_reset.48467289174494132812097880901556930084436502004997450616206694205239304308685
    Line 4456, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8999748641 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 8999748641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 4 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 4 failures.
  - 6.otp_ctrl_stress_all_with_rand_reset.8169621659425756880945274638495679571890930397744204926983253080603413061299
    Line 12773, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 137235469331 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1131035738 [0x436a3c5a] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 137235469331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 44.otp_ctrl_stress_all_with_rand_reset.37451353774751094156106221153789415817949740808116650486245671390669510074111
    Line 12926, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 112034498398 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4138466478 [0xf6abfcae] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 112034498398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 2 failures:

Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

14.otp_ctrl_stress_all_with_rand_reset.80388707287182823004130190663762846190069028296000248523555450174960694713226
Line 4070, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 2066421765 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 2066523805 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 2066585029 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 2067891141 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 2068115629 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

30.otp_ctrl_stress_all_with_rand_reset.113665762187287053789046934075004390697836221264820528797990446970441008389944
Line 775, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 2253488510 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 2253828510 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 2253848510 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 2254468510 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 2254488510 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 41.otp_ctrl_stress_all_with_rand_reset.2402111521935402173643159703063364803056386948005814013898047997124325825640
    Line 13466, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 64950613866 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 548 [0x224]) dai addr 224 rdata0 readout mismatch
  UVM_INFO @ 64950613866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 83.otp_ctrl_stress_all_with_rand_reset.86491130020239972106856793925032064543987433268001161460422594337549907870445
    Line 410, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/83.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7677003175 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1136 [0x470]) dai addr 470 rdata0 readout mismatch
  UVM_INFO @ 7677003175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 58.otp_ctrl_stress_all_with_rand_reset.62982439655204309620976262826532150339990299414743041545839999311274365388002
    Line 45870, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/58.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 202381643546 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 202381643546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 61.otp_ctrl_stress_all_with_rand_reset.30095690972108255553025518718160172118604944423064560869772195055606996208503
    Line 6164, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/61.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2068868588 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 2068868588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(cio_test_en_o == *)' has 1 failures:
- Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 9.otp_ctrl_csr_mem_rw_with_rand_reset.59396368351818760643852365721518257479190730828376756035797958906460754110633
    Line 267, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  28482396 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  28482396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```