OTP_CTRL Simulation Results

Saturday July 20 2024 23:02:34 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85433431889345478971181747401055702269263498582281270185582621732035232392187

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.760s	142.201us	1	1	100.00
V1	smoke	otp_ctrl_smoke	1.522m	12.424ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	3.050s	992.772us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.230s	700.652us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	8.270s	1.385ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.420s	310.137us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	5.640s	1.662ms	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.230s	700.652us	20	20	100.00
		otp_ctrl_csr_aliasing	6.420s	310.137us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.790s	531.740us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.340s	68.099us	5	5	100.00
V1		TOTAL			115	116	99.14
V2	dai_access_partition_walk	otp_ctrl_partition_walk	19.490s	627.964us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	7.930s	2.715ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	2.189m	16.985ms	10	10	100.00
		otp_ctrl_check_fail	45.690s	9.557ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	12.540s	4.426ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.616m	8.888ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.188m	8.753ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	32.110s	11.730ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	37.890s	5.683ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	56.780s	20.843ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.324m	93.023ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.288m	7.053ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	31.899m	175.881ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	1.980s	569.416us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.960s	1.090ms	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	6.640s	1.303ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	6.640s	1.303ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	3.050s	992.772us	5	5	100.00
		otp_ctrl_csr_rw	2.230s	700.652us	20	20	100.00
		otp_ctrl_csr_aliasing	6.420s	310.137us	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.030s	1.310ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	3.050s	992.772us	5	5	100.00
		otp_ctrl_csr_rw	2.230s	700.652us	20	20	100.00
		otp_ctrl_csr_aliasing	6.420s	310.137us	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.030s	1.310ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.398m	13.252ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.398m	13.252ms	5	5	100.00
		otp_ctrl_tl_intg_err	38.000s	20.257ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.398m	13.252ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.398m	13.252ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	38.000s	20.257ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	1.522m	12.424ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	1.522m	12.424ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.398m	13.252ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.398m	13.252ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.398m	13.252ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.398m	13.252ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.398m	13.252ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.398m	13.252ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.398m	13.252ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.398m	13.252ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.398m	13.252ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.398m	13.252ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.398m	13.252ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.398m	13.252ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.398m	13.252ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.398m	13.252ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.398m	13.252ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.890s	5.683ms	200	200	100.00
		otp_ctrl_sec_cm	3.398m	13.252ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.890s	5.683ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.890s	5.683ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.890s	5.683ms	200	200	100.00
		otp_ctrl_macro_errs	1.324m	93.023ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.890s	5.683ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.890s	5.683ms	200	200	100.00
		otp_ctrl_sec_cm	3.398m	13.252ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.890s	5.683ms	200	200	100.00
		otp_ctrl_sec_cm	3.398m	13.252ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.890s	5.683ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.890s	5.683ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.890s	5.683ms	200	200	100.00
		otp_ctrl_macro_errs	1.324m	93.023ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.890s	5.683ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.890s	5.683ms	200	200	100.00
		otp_ctrl_sec_cm	3.398m	13.252ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	7.930s	2.715ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	45.690s	9.557ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.616m	8.888ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.616m	8.888ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.616m	8.888ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.616m	8.888ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.616m	8.888ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	1.522m	12.424ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.616m	8.888ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	1.522m	12.424ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.398m	13.252ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	12.540s	4.426ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	1.522m	12.424ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	1.522m	12.424ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.324m	93.023ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	19.310s	5.912ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	59.698m	704.783ms	82	100	82.00
V3		TOTAL			83	101	82.18
		TOTAL			1324	1343	98.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.95	93.81	96.20	95.87	92.12	97.10	96.34	93.21

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 5 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 5 failures.

    • 3.otp_ctrl_stress_all_with_rand_reset.61189685390256002596383458611187774601450722747071905710498520233600521266978
      Line 14198, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 142341901013 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1297351523 [0x4d540363] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 142341901013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 18.otp_ctrl_stress_all_with_rand_reset.8863250585980017449924200302242824894984271918966603994586183507949815934660
      Line 32522, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 399306268769 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2425175175 [0x908d3c87] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 399306268769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 4 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 4 failures.

    • 25.otp_ctrl_stress_all_with_rand_reset.18409043112981054532978010466997066485302166306346553262276846455208923466979
      Line 51617, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 19417654274 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 19417654274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 29.otp_ctrl_stress_all_with_rand_reset.102095400872232836451808949720055468745604910397905828495061389276988828413923
      Line 8300, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 15306253860 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 15306253860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 3 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 3 failures.

    • 1.otp_ctrl_stress_all_with_rand_reset.52793217181677753136614247688124469109589392571805930129493008218572262198245
      Line 80037, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 28834046024 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 28834046024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 23.otp_ctrl_stress_all_with_rand_reset.28357782227154309603779588530794292921059053942360787470824294784932411197426
      Line 17731, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 29690383510 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 29690383510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• Offending '(cio_test_en_o == *)' has 2 failures:

  • Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 11.otp_ctrl_csr_mem_rw_with_rand_reset.101717326458827979558691695035487566562081928867172215382304622886816081076923
      Line 267, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @  33741621 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @  33741621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 81.otp_ctrl_stress_all_with_rand_reset.48555649188502847118724947914765612611901635289699000868251236263875390315873
      Line 5761, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/81.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 10818481621 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 10818481621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 13.otp_ctrl_stress_all_with_rand_reset.109861430482084658700334820475730334329759402285257735807325982442752699403248
      Line 2798, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 129960139262 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 30743866 [0x1d51d3a]) dai addr 784 rdata0 readout mismatch
        UVM_INFO @ 129960139262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c* rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 30.otp_ctrl_stress_all_with_rand_reset.108657238327672401472239516835608218429150957630860578166379097243140848238921
      Line 52211, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 38871417240 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1732 [0x6c4]) dai addr 6c4 rdata0 readout mismatch
        UVM_INFO @ 38871417240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 53.otp_ctrl_stress_all_with_rand_reset.96748430914981534008867326871824116009455824260388815457278242714385082746981
      Line 270, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/53.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3853277737 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 4096496118 [0xf42b91f6]) dai addr 76c rdata0 readout mismatch
        UVM_INFO @ 3853277737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.dai_idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=910) has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 75.otp_ctrl_stress_all_with_rand_reset.40558379703036409134109027396568028342200716167672321842184448935079299811553
      Line 88113, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/75.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 600758894521 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.dai_idle (addr=0xed84f010, Comparison=CompareOpEq, exp_data=0x1, call_count=910)
        UVM_INFO @ 600758894521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:277) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 83.otp_ctrl_stress_all_with_rand_reset.7395202805228231939956931471332945942251072076025346861236165464966448305540
      Line 55300, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/83.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 15269835467 ps: (otp_ctrl_scoreboard.sv:277) [uvm_test_top.env.scoreboard] Check failed exp_alert != OtpNoAlert (0 [0x0] vs 0 [0x0])
        UVM_INFO @ 15269835467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.07.20_09.51.21
• 2024.07.19_08.53.05
• 2024.07.18_09.24.35
• 2024.07.17_09.35.21
• 2024.07.16_09.41.52
• 2024.07.15_09.30.41