OTP_CTRL Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.920s	200.086us	1	1	100.00
V1	smoke	otp_ctrl_smoke	17.250s	5.622ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.530s	140.465us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.900s	567.269us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	9.050s	1.601ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	7.090s	3.117ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.940s	412.828us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.900s	567.269us	20	20	100.00
		otp_ctrl_csr_aliasing	7.090s	3.117ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	2.120s	535.790us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.360s	39.401us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	19.660s	611.748us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.270s	2.450ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	56.870s	7.327ms	10	10	100.00
		otp_ctrl_check_fail	2.033m	30.357ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	12.490s	488.588us	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.055m	23.231ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	46.020s	19.804ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	35.910s	10.242ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	28.220s	1.781ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.024m	17.096ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.062m	3.212ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	2.397m	18.823ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	9.106m	66.235ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.080s	601.117us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.940s	300.637us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.970s	906.958us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.970s	906.958us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.530s	140.465us	5	5	100.00
		otp_ctrl_csr_rw	1.900s	567.269us	20	20	100.00
		otp_ctrl_csr_aliasing	7.090s	3.117ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.910s	1.165ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.530s	140.465us	5	5	100.00
		otp_ctrl_csr_rw	1.900s	567.269us	20	20	100.00
		otp_ctrl_csr_aliasing	7.090s	3.117ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.910s	1.165ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.480m	170.441ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.480m	170.441ms	5	5	100.00
		otp_ctrl_tl_intg_err	42.760s	19.683ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.480m	170.441ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.480m	170.441ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	42.760s	19.683ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	17.250s	5.622ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	17.250s	5.622ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.480m	170.441ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.480m	170.441ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.480m	170.441ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.480m	170.441ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.480m	170.441ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.480m	170.441ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.480m	170.441ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.480m	170.441ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.480m	170.441ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.480m	170.441ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.480m	170.441ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.480m	170.441ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.480m	170.441ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.480m	170.441ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.480m	170.441ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	28.220s	1.781ms	200	200	100.00
		otp_ctrl_sec_cm	4.480m	170.441ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	28.220s	1.781ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	28.220s	1.781ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	28.220s	1.781ms	200	200	100.00
		otp_ctrl_macro_errs	1.062m	3.212ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	28.220s	1.781ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	28.220s	1.781ms	200	200	100.00
		otp_ctrl_sec_cm	4.480m	170.441ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	28.220s	1.781ms	200	200	100.00
		otp_ctrl_sec_cm	4.480m	170.441ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	28.220s	1.781ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	28.220s	1.781ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	28.220s	1.781ms	200	200	100.00
		otp_ctrl_macro_errs	1.062m	3.212ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	28.220s	1.781ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	28.220s	1.781ms	200	200	100.00
		otp_ctrl_sec_cm	4.480m	170.441ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.270s	2.450ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	2.033m	30.357ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.055m	23.231ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.055m	23.231ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.055m	23.231ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.055m	23.231ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.055m	23.231ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	17.250s	5.622ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.055m	23.231ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	17.250s	5.622ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.480m	170.441ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	12.490s	488.588us	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	17.250s	5.622ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	17.250s	5.622ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.062m	3.212ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	11.260s	6.008ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	46.589m	251.374ms	77	100	77.00
V3		TOTAL			78	101	77.23
		TOTAL			1320	1343	98.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.88	93.76	96.20	95.63	91.89	97.05	96.34	93.28

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 10 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 10 failures.
  - 14.otp_ctrl_stress_all_with_rand_reset.18928412005766316024302139582384978921978396883367779249247719934370184623704
    Line 9840, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 41196998673 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 41196998673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.otp_ctrl_stress_all_with_rand_reset.13923988084600845027144626842194181953061203751507024845382051034911011661297
    Line 13693, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 56556275781 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 56556275781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 4 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 4 failures.
  - 13.otp_ctrl_stress_all_with_rand_reset.35587749759712221784770110673229226606670651716696041564573653218966316373144
    Line 14378, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1398891080 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 1398891080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.otp_ctrl_stress_all_with_rand_reset.17302695608375655670596183996874977275711377732256770921953973326372916447740
    Line 50778, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 852060183543 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 852060183543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 2 failures:

Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

12.otp_ctrl_stress_all_with_rand_reset.38463812054125166790138886232920513794014969274212788841622420800321357748507
Line 37727, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 211107342452 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 211107842456 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 211107884123 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 211108675796 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 211108717463 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

62.otp_ctrl_stress_all_with_rand_reset.99495053830299090803315690652034848802111099969269046504749848124329219480625
Line 5915, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/62.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 2441234008 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 2441874008 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 2441914008 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 2443034008 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 2443074008 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 25.otp_ctrl_stress_all_with_rand_reset.36253754489021383821177747179417481609110499245853295985979040211562436196836
    Line 20938, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8002093652 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1306526488 [0x4de00318] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 8002093652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 97.otp_ctrl_stress_all_with_rand_reset.54214486804786045840340156112636301690594703105861199864827020790047227440110
    Line 41760, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/97.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 180398674694 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2063234989 [0x7afa77ad] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 180398674694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(cio_test_en_o == *)' has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 27.otp_ctrl_stress_all_with_rand_reset.81860225624873225373639726911859083551212998785489201835315828058598618836935
    Line 14134, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 36472964427 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 36472964427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 28.otp_ctrl_stress_all_with_rand_reset.27408670040450108189773912146503837297814968601667250046405885356889357080080
    Line 53163, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 82502608982 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 82502608982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:839) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 36.otp_ctrl_stress_all_with_rand_reset.62899674801759203096555291000325252393225605007712943785790666289254049052432
    Line 17279, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4083738779 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4083738779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 80.otp_ctrl_stress_all_with_rand_reset.106001713075818492184782112932787730846845556268185052873952234344882349412231
    Line 68085, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/80.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 85233999134 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 85233999134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.dai_idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=647) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 78.otp_ctrl_stress_all_with_rand_reset.97228762471165586160424275855708583196936488476131500206208827958653725975105
    Line 72054, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/78.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 210985466748 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.dai_idle (addr=0xb772c010, Comparison=CompareOpEq, exp_data=0x1, call_count=647)
  UVM_INFO @ 210985466748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```