OTP_CTRL Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: 3e0219a2c5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	2.140s	726.717us	1	1	100.00
V1	smoke	otp_ctrl_smoke	13.500s	5.916ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	3.070s	1.025ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.950s	173.900us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	11.190s	1.481ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	5.880s	650.726us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	6.070s	1.655ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.950s	173.900us	20	20	100.00
		otp_ctrl_csr_aliasing	5.880s	650.726us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.490s	144.764us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.430s	60.558us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	18.350s	1.495ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.560s	2.636ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	1.307m	7.625ms	10	10	100.00
		otp_ctrl_check_fail	1.728m	10.571ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	14.430s	4.681ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.141m	21.870ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	45.410s	15.719ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	40.680s	12.312ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	32.000s	11.963ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.298m	25.528ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.450m	24.554ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.137m	7.243ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	6.676m	145.893ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.110s	559.596us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.200s	247.474us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.540s	208.572us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.540s	208.572us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	3.070s	1.025ms	5	5	100.00
		otp_ctrl_csr_rw	1.950s	173.900us	20	20	100.00
		otp_ctrl_csr_aliasing	5.880s	650.726us	5	5	100.00
		otp_ctrl_same_csr_outstanding	6.360s	1.897ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	3.070s	1.025ms	5	5	100.00
		otp_ctrl_csr_rw	1.950s	173.900us	20	20	100.00
		otp_ctrl_csr_aliasing	5.880s	650.726us	5	5	100.00
		otp_ctrl_same_csr_outstanding	6.360s	1.897ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.580m	41.537ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.580m	41.537ms	5	5	100.00
		otp_ctrl_tl_intg_err	22.460s	4.774ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.580m	41.537ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.580m	41.537ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	22.460s	4.774ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	13.500s	5.916ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	13.500s	5.916ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.580m	41.537ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.580m	41.537ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.580m	41.537ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.580m	41.537ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.580m	41.537ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.580m	41.537ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.580m	41.537ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.580m	41.537ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.580m	41.537ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.580m	41.537ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.580m	41.537ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.580m	41.537ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.580m	41.537ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.580m	41.537ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.580m	41.537ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.000s	11.963ms	200	200	100.00
		otp_ctrl_sec_cm	4.580m	41.537ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.000s	11.963ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.000s	11.963ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.000s	11.963ms	200	200	100.00
		otp_ctrl_macro_errs	1.450m	24.554ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.000s	11.963ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.000s	11.963ms	200	200	100.00
		otp_ctrl_sec_cm	4.580m	41.537ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.000s	11.963ms	200	200	100.00
		otp_ctrl_sec_cm	4.580m	41.537ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.000s	11.963ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.000s	11.963ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.000s	11.963ms	200	200	100.00
		otp_ctrl_macro_errs	1.450m	24.554ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.000s	11.963ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.000s	11.963ms	200	200	100.00
		otp_ctrl_sec_cm	4.580m	41.537ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.560s	2.636ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.728m	10.571ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.141m	21.870ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.141m	21.870ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.141m	21.870ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.141m	21.870ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.141m	21.870ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	13.500s	5.916ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.141m	21.870ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	13.500s	5.916ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.580m	41.537ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	14.430s	4.681ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	13.500s	5.916ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	13.500s	5.916ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.450m	24.554ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	10.850s	7.041ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.328h	1.422s	83	100	83.00
V3		TOTAL			84	101	83.17
		TOTAL			1326	1343	98.73

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.01	93.78	96.70	96.00	91.65	97.24	96.34	93.35

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 7 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 7 failures.

    • 0.otp_ctrl_stress_all_with_rand_reset.98186869949953244250093650302184944994952323283006987454854026780339144733141
      Line 40813, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6616165985 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (13710581 [0xd134f5] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 6616165985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 13.otp_ctrl_stress_all_with_rand_reset.17001575891958223748166530192158554077272027475585759088074037016629750378709
      Line 49486, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 67420517196 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (914393799 [0x36808ac7] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 67420517196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 7 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 7 failures.

    • 5.otp_ctrl_stress_all_with_rand_reset.8239722314818252619327330581527041797341800416474150897975069715878359202468
      Line 51304, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1112425750928 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 1112425750928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 9.otp_ctrl_stress_all_with_rand_reset.74138021405173451011827658312537533699912907096713617668139172523374789380267
      Line 4558, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 72935309991 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 72935309991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 4.otp_ctrl_stress_all_with_rand_reset.103687341288712827314943487929281752228622823471968487969092190357163313844786
      Line 21274, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9196753320 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 9196753320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(cio_test_en_o == *)' has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 58.otp_ctrl_stress_all_with_rand_reset.74237757752478128631015262074144070171816317835636171636133095925178775129321
      Line 11114, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/58.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 444584798 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 444584798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 66.otp_ctrl_stress_all_with_rand_reset.20527215163384453491596589448399230856303401219891799461780409161452850945293
      Line 13178, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/66.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12608815761 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0
        UVM_INFO @ 12608815761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.07.22_08.47.38
• 2024.07.21_08.27.57
• 2024.07.20_09.51.21
• 2024.07.19_08.53.05
• 2024.07.18_09.24.35
• 2024.07.17_09.35.21