OTP_CTRL Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: 0bfa990ddc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 wake_up otp_ctrl_wake_up 1.700s 783.124us 1 1 100.00
V1 smoke otp_ctrl_smoke 24.950s 4.482ms 50 50 100.00
V1 csr_hw_reset otp_ctrl_csr_hw_reset 2.730s 241.389us 5 5 100.00
V1 csr_rw otp_ctrl_csr_rw 2.160s 610.634us 20 20 100.00
V1 csr_bit_bash otp_ctrl_csr_bit_bash 10.630s 1.680ms 5 5 100.00
V1 csr_aliasing otp_ctrl_csr_aliasing 6.100s 196.491us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otp_ctrl_csr_mem_rw_with_rand_reset 4.550s 1.649ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr otp_ctrl_csr_rw 2.160s 610.634us 20 20 100.00
otp_ctrl_csr_aliasing 6.100s 196.491us 5 5 100.00
V1 mem_walk otp_ctrl_mem_walk 1.920s 500.912us 5 5 100.00
V1 mem_partial_access otp_ctrl_mem_partial_access 1.740s 505.890us 5 5 100.00
V1 TOTAL 116 116 100.00
V2 dai_access_partition_walk otp_ctrl_partition_walk 19.700s 1.569ms 1 1 100.00
V2 init_fail otp_ctrl_init_fail 8.660s 2.367ms 300 300 100.00
V2 partition_check otp_ctrl_background_chks 27.200s 1.604ms 10 10 100.00
otp_ctrl_check_fail 32.150s 1.355ms 50 50 100.00
V2 regwen_during_otp_init otp_ctrl_regwen 11.070s 989.306us 50 50 100.00
V2 partition_lock otp_ctrl_dai_lock 1.644m 16.187ms 50 50 100.00
V2 interface_key_check otp_ctrl_parallel_key_req 45.880s 6.728ms 50 50 100.00
V2 lc_interactions otp_ctrl_parallel_lc_req 46.790s 14.141ms 50 50 100.00
otp_ctrl_parallel_lc_esc 37.850s 15.845ms 200 200 100.00
V2 otp_dai_errors otp_ctrl_dai_errs 35.370s 3.937ms 50 50 100.00
V2 otp_macro_errors otp_ctrl_macro_errs 1.484m 13.910ms 50 50 100.00
V2 test_access otp_ctrl_test_access 56.090s 4.109ms 50 50 100.00
V2 stress_all otp_ctrl_stress_all 9.819m 209.305ms 50 50 100.00
V2 intr_test otp_ctrl_intr_test 1.890s 549.744us 50 50 100.00
V2 alert_test otp_ctrl_alert_test 3.000s 213.990us 50 50 100.00
V2 tl_d_oob_addr_access otp_ctrl_tl_errors 9.380s 2.821ms 20 20 100.00
V2 tl_d_illegal_access otp_ctrl_tl_errors 9.380s 2.821ms 20 20 100.00
V2 tl_d_outstanding_access otp_ctrl_csr_hw_reset 2.730s 241.389us 5 5 100.00
otp_ctrl_csr_rw 2.160s 610.634us 20 20 100.00
otp_ctrl_csr_aliasing 6.100s 196.491us 5 5 100.00
otp_ctrl_same_csr_outstanding 3.730s 166.957us 20 20 100.00
V2 tl_d_partial_access otp_ctrl_csr_hw_reset 2.730s 241.389us 5 5 100.00
otp_ctrl_csr_rw 2.160s 610.634us 20 20 100.00
otp_ctrl_csr_aliasing 6.100s 196.491us 5 5 100.00
otp_ctrl_same_csr_outstanding 3.730s 166.957us 20 20 100.00
V2 TOTAL 1101 1101 100.00
V2S sec_cm_additional_check otp_ctrl_sec_cm 3.391m 38.697ms 5 5 100.00
V2S tl_intg_err otp_ctrl_sec_cm 3.391m 38.697ms 5 5 100.00
otp_ctrl_tl_intg_err 22.870s 4.637ms 20 20 100.00
V2S prim_count_check otp_ctrl_sec_cm 3.391m 38.697ms 5 5 100.00
V2S prim_fsm_check otp_ctrl_sec_cm 3.391m 38.697ms 5 5 100.00
V2S sec_cm_bus_integrity otp_ctrl_tl_intg_err 22.870s 4.637ms 20 20 100.00
V2S sec_cm_secret_mem_scramble otp_ctrl_smoke 24.950s 4.482ms 50 50 100.00
V2S sec_cm_part_mem_digest otp_ctrl_smoke 24.950s 4.482ms 50 50 100.00
V2S sec_cm_dai_fsm_sparse otp_ctrl_sec_cm 3.391m 38.697ms 5 5 100.00
V2S sec_cm_kdi_fsm_sparse otp_ctrl_sec_cm 3.391m 38.697ms 5 5 100.00
V2S sec_cm_lci_fsm_sparse otp_ctrl_sec_cm 3.391m 38.697ms 5 5 100.00
V2S sec_cm_part_fsm_sparse otp_ctrl_sec_cm 3.391m 38.697ms 5 5 100.00
V2S sec_cm_scrmbl_fsm_sparse otp_ctrl_sec_cm 3.391m 38.697ms 5 5 100.00
V2S sec_cm_timer_fsm_sparse otp_ctrl_sec_cm 3.391m 38.697ms 5 5 100.00
V2S sec_cm_dai_ctr_redun otp_ctrl_sec_cm 3.391m 38.697ms 5 5 100.00
V2S sec_cm_kdi_seed_ctr_redun otp_ctrl_sec_cm 3.391m 38.697ms 5 5 100.00
V2S sec_cm_kdi_entropy_ctr_redun otp_ctrl_sec_cm 3.391m 38.697ms 5 5 100.00
V2S sec_cm_lci_ctr_redun otp_ctrl_sec_cm 3.391m 38.697ms 5 5 100.00
V2S sec_cm_part_ctr_redun otp_ctrl_sec_cm 3.391m 38.697ms 5 5 100.00
V2S sec_cm_scrmbl_ctr_redun otp_ctrl_sec_cm 3.391m 38.697ms 5 5 100.00
V2S sec_cm_timer_integ_ctr_redun otp_ctrl_sec_cm 3.391m 38.697ms 5 5 100.00
V2S sec_cm_timer_cnsty_ctr_redun otp_ctrl_sec_cm 3.391m 38.697ms 5 5 100.00
V2S sec_cm_timer_lfsr_redun otp_ctrl_sec_cm 3.391m 38.697ms 5 5 100.00
V2S sec_cm_dai_fsm_local_esc otp_ctrl_parallel_lc_esc 37.850s 15.845ms 200 200 100.00
otp_ctrl_sec_cm 3.391m 38.697ms 5 5 100.00
V2S sec_cm_lci_fsm_local_esc otp_ctrl_parallel_lc_esc 37.850s 15.845ms 200 200 100.00
V2S sec_cm_kdi_fsm_local_esc otp_ctrl_parallel_lc_esc 37.850s 15.845ms 200 200 100.00
V2S sec_cm_part_fsm_local_esc otp_ctrl_parallel_lc_esc 37.850s 15.845ms 200 200 100.00
otp_ctrl_macro_errs 1.484m 13.910ms 50 50 100.00
V2S sec_cm_scrmbl_fsm_local_esc otp_ctrl_parallel_lc_esc 37.850s 15.845ms 200 200 100.00
V2S sec_cm_timer_fsm_local_esc otp_ctrl_parallel_lc_esc 37.850s 15.845ms 200 200 100.00
otp_ctrl_sec_cm 3.391m 38.697ms 5 5 100.00
V2S sec_cm_dai_fsm_global_esc otp_ctrl_parallel_lc_esc 37.850s 15.845ms 200 200 100.00
otp_ctrl_sec_cm 3.391m 38.697ms 5 5 100.00
V2S sec_cm_lci_fsm_global_esc otp_ctrl_parallel_lc_esc 37.850s 15.845ms 200 200 100.00
V2S sec_cm_kdi_fsm_global_esc otp_ctrl_parallel_lc_esc 37.850s 15.845ms 200 200 100.00
V2S sec_cm_part_fsm_global_esc otp_ctrl_parallel_lc_esc 37.850s 15.845ms 200 200 100.00
otp_ctrl_macro_errs 1.484m 13.910ms 50 50 100.00
V2S sec_cm_scrmbl_fsm_global_esc otp_ctrl_parallel_lc_esc 37.850s 15.845ms 200 200 100.00
V2S sec_cm_timer_fsm_global_esc otp_ctrl_parallel_lc_esc 37.850s 15.845ms 200 200 100.00
otp_ctrl_sec_cm 3.391m 38.697ms 5 5 100.00
V2S sec_cm_part_data_reg_integrity otp_ctrl_init_fail 8.660s 2.367ms 300 300 100.00
V2S sec_cm_part_data_reg_bkgn_chk otp_ctrl_check_fail 32.150s 1.355ms 50 50 100.00
V2S sec_cm_part_mem_regren otp_ctrl_dai_lock 1.644m 16.187ms 50 50 100.00
V2S sec_cm_part_mem_sw_unreadable otp_ctrl_dai_lock 1.644m 16.187ms 50 50 100.00
V2S sec_cm_part_mem_sw_unwritable otp_ctrl_dai_lock 1.644m 16.187ms 50 50 100.00
V2S sec_cm_lc_part_mem_sw_noaccess otp_ctrl_dai_lock 1.644m 16.187ms 50 50 100.00
V2S sec_cm_access_ctrl_mubi otp_ctrl_dai_lock 1.644m 16.187ms 50 50 100.00
V2S sec_cm_token_valid_ctrl_mubi otp_ctrl_smoke 24.950s 4.482ms 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi otp_ctrl_dai_lock 1.644m 16.187ms 50 50 100.00
V2S sec_cm_test_bus_lc_gated otp_ctrl_smoke 24.950s 4.482ms 50 50 100.00
V2S sec_cm_test_tl_lc_gate_fsm_sparse otp_ctrl_sec_cm 3.391m 38.697ms 5 5 100.00
V2S sec_cm_direct_access_config_regwen otp_ctrl_regwen 11.070s 989.306us 50 50 100.00
V2S sec_cm_check_trigger_config_regwen otp_ctrl_smoke 24.950s 4.482ms 50 50 100.00
V2S sec_cm_check_config_regwen otp_ctrl_smoke 24.950s 4.482ms 50 50 100.00
V2S sec_cm_macro_mem_integrity otp_ctrl_macro_errs 1.484m 13.910ms 50 50 100.00
V2S TOTAL 25 25 100.00
V3 otp_ctrl_low_freq_read otp_ctrl_low_freq_read 13.320s 3.033ms 1 1 100.00
V3 stress_all_with_rand_reset otp_ctrl_stress_all_with_rand_reset 1.421h 345.905ms 87 100 87.00
V3 TOTAL 88 101 87.13
TOTAL 1330 1343 99.03

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 17 17 17 100.00
V2S 2 2 2 100.00
V3 2 2 1 50.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.97 93.81 96.65 96.02 91.41 97.24 96.34 93.35

Failure Buckets

Past Results