OTP_CTRL Simulation Results

Wednesday July 24 2024 23:04:46 UTC

GitHub Revision: e439226b6c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80778109121175195808319778278610424989650974127729484509360263424111433728567

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	2.380s	784.883us	1	1	100.00
V1	smoke	otp_ctrl_smoke	14.570s	2.271ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	3.160s	1.432ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.950s	556.614us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	9.730s	486.199us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	5.830s	1.579ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	5.150s	1.637ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.950s	556.614us	20	20	100.00
		otp_ctrl_csr_aliasing	5.830s	1.579ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.480s	535.811us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.460s	37.334us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	21.960s	5.113ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	10.030s	3.001ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	21.690s	12.069ms	10	10	100.00
		otp_ctrl_check_fail	1.080m	6.682ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	14.630s	3.748ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	58.750s	9.775ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	42.530s	12.788ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	37.900s	11.659ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	27.580s	1.363ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	47.410s	5.796ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	54.840s	3.664ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	3.477m	27.186ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	5.522m	23.127ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.190s	524.268us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.600s	983.084us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	9.720s	3.051ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	9.720s	3.051ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	3.160s	1.432ms	5	5	100.00
		otp_ctrl_csr_rw	1.950s	556.614us	20	20	100.00
		otp_ctrl_csr_aliasing	5.830s	1.579ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.770s	2.167ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	3.160s	1.432ms	5	5	100.00
		otp_ctrl_csr_rw	1.950s	556.614us	20	20	100.00
		otp_ctrl_csr_aliasing	5.830s	1.579ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.770s	2.167ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	5.726m	172.892ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	5.726m	172.892ms	5	5	100.00
		otp_ctrl_tl_intg_err	26.100s	19.950ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	5.726m	172.892ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	5.726m	172.892ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	26.100s	19.950ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	14.570s	2.271ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	14.570s	2.271ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	5.726m	172.892ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	5.726m	172.892ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	5.726m	172.892ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	5.726m	172.892ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	5.726m	172.892ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	5.726m	172.892ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	5.726m	172.892ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	5.726m	172.892ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	5.726m	172.892ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	5.726m	172.892ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	5.726m	172.892ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	5.726m	172.892ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	5.726m	172.892ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	5.726m	172.892ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	5.726m	172.892ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	27.580s	1.363ms	200	200	100.00
		otp_ctrl_sec_cm	5.726m	172.892ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	27.580s	1.363ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	27.580s	1.363ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	27.580s	1.363ms	200	200	100.00
		otp_ctrl_macro_errs	54.840s	3.664ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	27.580s	1.363ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	27.580s	1.363ms	200	200	100.00
		otp_ctrl_sec_cm	5.726m	172.892ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	27.580s	1.363ms	200	200	100.00
		otp_ctrl_sec_cm	5.726m	172.892ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	27.580s	1.363ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	27.580s	1.363ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	27.580s	1.363ms	200	200	100.00
		otp_ctrl_macro_errs	54.840s	3.664ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	27.580s	1.363ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	27.580s	1.363ms	200	200	100.00
		otp_ctrl_sec_cm	5.726m	172.892ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	10.030s	3.001ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.080m	6.682ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	58.750s	9.775ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	58.750s	9.775ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	58.750s	9.775ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	58.750s	9.775ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	58.750s	9.775ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	14.570s	2.271ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	58.750s	9.775ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	14.570s	2.271ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	5.726m	172.892ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	14.630s	3.748ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	14.570s	2.271ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	14.570s	2.271ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	54.840s	3.664ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	16.370s	5.979ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	58.807m	387.666ms	82	100	82.00
V3		TOTAL			83	101	82.18
		TOTAL			1325	1343	98.66

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.01	93.81	96.67	95.97	91.65	97.24	96.34	93.35

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 6 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 6 failures.

    • 13.otp_ctrl_stress_all_with_rand_reset.54466779415208567793747321603525797513977383321620832707012592453667220299852
      Line 37045, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 73490902171 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 73490902171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 46.otp_ctrl_stress_all_with_rand_reset.93219985056976079272190976199202683461142762914014004940293339135410917840798
      Line 3671, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 663675806 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 663675806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 4 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 4 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 4 failures.

    • 0.otp_ctrl_stress_all_with_rand_reset.32198372544282184840421721843815078185878806397153046276647973773827984564694
      Line 50921, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 15993877735 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (583918515 [0x22cde3b3] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 15993877735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 19.otp_ctrl_stress_all_with_rand_reset.35618247641032910884959672550037231252881509182195444366081178470394351474723
      Line 4183, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 160144039543 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1617868777 [0x606eb7e9] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 160144039543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_ERROR (cip_base_vseq.sv:839) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

    • 66.otp_ctrl_stress_all_with_rand_reset.38536373433951277500997015528449280071128589306466629545669583370964824341180
      Line 10500, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/66.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 480935083495 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 480935083495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 89.otp_ctrl_stress_all_with_rand_reset.32639655142773303620470838747316392433918074044426707203742107636768259654107
      Line 152215, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/89.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1185535814735 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1185535814735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 12.otp_ctrl_stress_all_with_rand_reset.91539057584759031454991944216381397548213742449150111196278402481846942756454
      Line 81936, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 475099564543 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 856 [0x358]) dai addr 358 rdata0 readout mismatch
        UVM_INFO @ 475099564543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 25.otp_ctrl_stress_all_with_rand_reset.95448445442847261608011140848133415865455715892167812249361170530339779887817
      Line 79514, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 22481821045 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 22481821045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:277) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 31.otp_ctrl_stress_all_with_rand_reset.32317259021140220220827356503607066289622513590397644157613617125127022053802
      Line 7728, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 36415783427 ps: (otp_ctrl_scoreboard.sv:277) [uvm_test_top.env.scoreboard] Check failed exp_alert != OtpNoAlert (0 [0x0] vs 0 [0x0])
        UVM_INFO @ 36415783427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(cio_test_en_o == *)' has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 73.otp_ctrl_stress_all_with_rand_reset.39150234644931704949259351221041708359946618742810802003027168307702789725249
      Line 30505, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/73.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 17204644881 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 17204644881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *f* rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 74.otp_ctrl_stress_all_with_rand_reset.74113100106082785756987012124062978778351998666517106960693540430402488017429
      Line 14876, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/74.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 13586397181 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 752 [0x2f0]) dai addr 2f0 rdata0 readout mismatch
        UVM_INFO @ 13586397181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=81) has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 77.otp_ctrl_stress_all_with_rand_reset.413905223539135426625716959196601577760801978737282036706407639585675174905
      Line 15404, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/77.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 19731499018 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=0x65b22010, Comparison=CompareOpEq, exp_data=0x0, call_count=81)
        UVM_INFO @ 19731499018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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