OTP_CTRL Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: `a47820eb4c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.640s	93.373us	1	1	100.00
V1	smoke	otp_ctrl_smoke	18.250s	5.590ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.540s	368.984us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.110s	618.435us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	10.290s	933.599us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	7.210s	2.538ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.400s	401.986us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.110s	618.435us	20	20	100.00
		otp_ctrl_csr_aliasing	7.210s	2.538ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.710s	565.089us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.860s	559.159us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	17.150s	2.129ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.180s	3.039ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	51.280s	4.709ms	10	10	100.00
		otp_ctrl_check_fail	51.630s	25.313ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	15.750s	4.372ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.030m	26.823ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.792m	5.611ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	44.240s	12.225ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	42.450s	15.905ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.064m	23.172ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.378m	27.394ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	49.970s	19.563ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	8.067m	125.721ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	1.810s	603.194us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.600s	320.581us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	9.960s	2.726ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	9.960s	2.726ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.540s	368.984us	5	5	100.00
		otp_ctrl_csr_rw	2.110s	618.435us	20	20	100.00
		otp_ctrl_csr_aliasing	7.210s	2.538ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.340s	1.710ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.540s	368.984us	5	5	100.00
		otp_ctrl_csr_rw	2.110s	618.435us	20	20	100.00
		otp_ctrl_csr_aliasing	7.210s	2.538ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.340s	1.710ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.709m	34.284ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.709m	34.284ms	5	5	100.00
		otp_ctrl_tl_intg_err	24.640s	20.305ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.709m	34.284ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.709m	34.284ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	24.640s	20.305ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	18.250s	5.590ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	18.250s	5.590ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.709m	34.284ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.709m	34.284ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.709m	34.284ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.709m	34.284ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.709m	34.284ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.709m	34.284ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.709m	34.284ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.709m	34.284ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.709m	34.284ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.709m	34.284ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.709m	34.284ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.709m	34.284ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.709m	34.284ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.709m	34.284ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.709m	34.284ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.450s	15.905ms	200	200	100.00
		otp_ctrl_sec_cm	3.709m	34.284ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.450s	15.905ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.450s	15.905ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.450s	15.905ms	200	200	100.00
		otp_ctrl_macro_errs	1.378m	27.394ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.450s	15.905ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.450s	15.905ms	200	200	100.00
		otp_ctrl_sec_cm	3.709m	34.284ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.450s	15.905ms	200	200	100.00
		otp_ctrl_sec_cm	3.709m	34.284ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.450s	15.905ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.450s	15.905ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.450s	15.905ms	200	200	100.00
		otp_ctrl_macro_errs	1.378m	27.394ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.450s	15.905ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.450s	15.905ms	200	200	100.00
		otp_ctrl_sec_cm	3.709m	34.284ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.180s	3.039ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	51.630s	25.313ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.030m	26.823ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.030m	26.823ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.030m	26.823ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.030m	26.823ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.030m	26.823ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	18.250s	5.590ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.030m	26.823ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	18.250s	5.590ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.709m	34.284ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	15.750s	4.372ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	18.250s	5.590ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	18.250s	5.590ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.378m	27.394ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	15.880s	7.538ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	58.350m	1.181s	85	100	85.00
V3		TOTAL			86	101	85.15
		TOTAL			1328	1343	98.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.73	93.79	96.18	95.63	90.93	97.05	96.34	93.21

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 7 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 7 failures.
  - 1.otp_ctrl_stress_all_with_rand_reset.115748132562976707668226894326545348692968805098724739079723035129484209626683
    Line 8387, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17009282945 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 17009282945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.otp_ctrl_stress_all_with_rand_reset.16023701429655886842263304865821924405631842402896698055998855451511079681876
    Line 37596, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 764949633468 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 764949633468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 4 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 4 failures.
  - 3.otp_ctrl_stress_all_with_rand_reset.108109089849618566229713959508433843037937662593565646654863484294457067725554
    Line 338, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  48032969 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (21305338 [0x14517fa] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @  48032969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.otp_ctrl_stress_all_with_rand_reset.65455722668029714639457000596182318584337899442672845818166041209162545814949
    Line 56854, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 211639678383 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2761987307 [0xa4a094eb] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 211639678383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 4.otp_ctrl_stress_all_with_rand_reset.1336539380632761856202702942918783712444871694728198572044920717535502426798
    Line 29401, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20435010929 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1128 [0x468]) dai addr 468 rdata0 readout mismatch
  UVM_INFO @ 20435010929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 9.otp_ctrl_stress_all_with_rand_reset.64269537175396461472677165076055767245570602195719444334194027825327613293629
    Line 56489, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 56845886426 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0
  UVM_INFO @ 56845886426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.dai_idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=320) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 16.otp_ctrl_stress_all_with_rand_reset.92931562935344661669639940476891912689987414080910871636444001129357222401805
    Line 54883, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 65578268222 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.dai_idle (addr=0x7ce75010, Comparison=CompareOpEq, exp_data=0x1, call_count=320)
  UVM_INFO @ 65578268222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

39.otp_ctrl_stress_all_with_rand_reset.88568103187961931065629523986146515916619497613041615752631940226377268407329
Line 7752, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 221047990323 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 221048323657 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 221345324251 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 221346990921 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 221347490922 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1