OTP_CTRL Simulation Results

Friday July 26 2024 23:02:17 UTC

GitHub Revision: `4877b481e8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 32772136499307530671572864311472020383177374948143841887013058662761887638244

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.700s	75.264us	1	1	100.00
V1	smoke	otp_ctrl_smoke	39.190s	5.395ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.940s	194.900us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.590s	633.008us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	6.430s	456.636us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.940s	615.407us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	5.790s	1.613ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.590s	633.008us	20	20	100.00
		otp_ctrl_csr_aliasing	6.940s	615.407us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	2.080s	512.409us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.770s	515.717us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	18.350s	322.980us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.840s	2.509ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	20.850s	2.065ms	10	10	100.00
		otp_ctrl_check_fail	53.830s	4.097ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	12.550s	364.044us	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.019m	14.345ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	51.780s	21.364ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	29.180s	9.590ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	36.320s	11.810ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	59.530s	22.584ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	47.600s	2.001ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	45.480s	3.257ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	10.152m	75.603ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.000s	520.107us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.260s	247.662us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	6.070s	145.813us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	6.070s	145.813us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.940s	194.900us	5	5	100.00
		otp_ctrl_csr_rw	2.590s	633.008us	20	20	100.00
		otp_ctrl_csr_aliasing	6.940s	615.407us	5	5	100.00
		otp_ctrl_same_csr_outstanding	6.270s	1.870ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.940s	194.900us	5	5	100.00
		otp_ctrl_csr_rw	2.590s	633.008us	20	20	100.00
		otp_ctrl_csr_aliasing	6.940s	615.407us	5	5	100.00
		otp_ctrl_same_csr_outstanding	6.270s	1.870ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.979m	42.601ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.979m	42.601ms	5	5	100.00
		otp_ctrl_tl_intg_err	25.520s	5.128ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.979m	42.601ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.979m	42.601ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	25.520s	5.128ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	39.190s	5.395ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	39.190s	5.395ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.979m	42.601ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.979m	42.601ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.979m	42.601ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.979m	42.601ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.979m	42.601ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.979m	42.601ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.979m	42.601ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.979m	42.601ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.979m	42.601ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.979m	42.601ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.979m	42.601ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.979m	42.601ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.979m	42.601ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.979m	42.601ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.979m	42.601ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.320s	11.810ms	200	200	100.00
		otp_ctrl_sec_cm	3.979m	42.601ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.320s	11.810ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.320s	11.810ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.320s	11.810ms	200	200	100.00
		otp_ctrl_macro_errs	47.600s	2.001ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.320s	11.810ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.320s	11.810ms	200	200	100.00
		otp_ctrl_sec_cm	3.979m	42.601ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.320s	11.810ms	200	200	100.00
		otp_ctrl_sec_cm	3.979m	42.601ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.320s	11.810ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.320s	11.810ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.320s	11.810ms	200	200	100.00
		otp_ctrl_macro_errs	47.600s	2.001ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.320s	11.810ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.320s	11.810ms	200	200	100.00
		otp_ctrl_sec_cm	3.979m	42.601ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.840s	2.509ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	53.830s	4.097ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.019m	14.345ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.019m	14.345ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.019m	14.345ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.019m	14.345ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.019m	14.345ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	39.190s	5.395ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.019m	14.345ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	39.190s	5.395ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.979m	42.601ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	12.550s	364.044us	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	39.190s	5.395ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	39.190s	5.395ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	47.600s	2.001ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	19.600s	6.994ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.249h	2.068s	83	100	83.00
V3		TOTAL			84	101	83.17
		TOTAL			1326	1343	98.73

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.92	93.76	96.15	95.69	92.12	97.00	96.34	93.35

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 7 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 7 failures.
  - 21.otp_ctrl_stress_all_with_rand_reset.109517299550126599479283268594388375733240212511215737505813923741393707422254
    Line 64994, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 131385476316 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2267355850 [0x87251aca] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 131385476316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 25.otp_ctrl_stress_all_with_rand_reset.94571764016930073714860362282318815917422519864140742346110119790290329560799
    Line 82779, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1266214608837 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2815300874 [0xa7ce150a] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 1266214608837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 5 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 5 failures.
  - 16.otp_ctrl_stress_all_with_rand_reset.112370463496743653429662165580037834559628489363437217694691586749664996101070
    Line 3384, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 602524787 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 602524787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 80.otp_ctrl_stress_all_with_rand_reset.111801118952815226499818423964257904189116376722232727548859766793456683181751
    Line 27146, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/80.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 122448984665 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 122448984665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 2 failures:

Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

33.otp_ctrl_stress_all_with_rand_reset.22244542020771345844316558792306005518417466432325171089870009031976313116201
Line 27211, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 80094378948 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 80094795618 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 80094837285 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 80096253963 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 80096295630 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

76.otp_ctrl_stress_all_with_rand_reset.65014426101575814038749094554683530774063029714464663318003923259222762867722
Line 19081, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/76.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 21890530032 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 21890630032 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 21890640032 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 21890930032 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 21890940032 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 3.otp_ctrl_stress_all_with_rand_reset.50708364644968109943626842991975354390517387978864420903347864073156913437518
    Line 3231, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 371672604 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 371672604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(cio_test_en_o == *)' has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 28.otp_ctrl_stress_all_with_rand_reset.3703530647311402297487088020627602867962097959436546644178692093990112380425
    Line 9662, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 114955064107 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 114955064107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 37.otp_ctrl_stress_all_with_rand_reset.114717408542677880720624223640000749626693857898300682307990412355748523982464
    Line 20890, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 21408209496 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 840 [0x348]) dai addr 348 rdata0 readout mismatch
  UVM_INFO @ 21408209496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```