OTP_CTRL Simulation Results

Saturday July 27 2024 23:02:25 UTC

GitHub Revision: `eca25c0ff8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 6528518538521148567139195500524222710943459299328477504124649113671643189924

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.800s	52.498us	1	1	100.00
V1	smoke	otp_ctrl_smoke	19.540s	16.502ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.920s	395.691us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.190s	569.886us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	8.830s	562.462us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	5.040s	85.158us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	3.940s	215.966us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.190s	569.886us	20	20	100.00
		otp_ctrl_csr_aliasing	5.040s	85.158us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	2.140s	542.374us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.460s	138.895us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	22.430s	5.096ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	7.970s	2.525ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	27.270s	1.506ms	10	10	100.00
		otp_ctrl_check_fail	1.216m	15.000ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	15.570s	4.676ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.030m	25.651ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	42.690s	4.166ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	40.860s	12.234ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	26.820s	3.755ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.114m	19.740ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.266m	24.559ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.663m	22.247ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	6.125m	86.586ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.510s	639.216us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.170s	879.870us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	8.380s	2.405ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	8.380s	2.405ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.920s	395.691us	5	5	100.00
		otp_ctrl_csr_rw	2.190s	569.886us	20	20	100.00
		otp_ctrl_csr_aliasing	5.040s	85.158us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.620s	263.797us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.920s	395.691us	5	5	100.00
		otp_ctrl_csr_rw	2.190s	569.886us	20	20	100.00
		otp_ctrl_csr_aliasing	5.040s	85.158us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.620s	263.797us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	7.418m	154.868ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	7.418m	154.868ms	5	5	100.00
		otp_ctrl_tl_intg_err	33.940s	20.303ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	7.418m	154.868ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	7.418m	154.868ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	33.940s	20.303ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	19.540s	16.502ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	19.540s	16.502ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	7.418m	154.868ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	7.418m	154.868ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	7.418m	154.868ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	7.418m	154.868ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	7.418m	154.868ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	7.418m	154.868ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	7.418m	154.868ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	7.418m	154.868ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	7.418m	154.868ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	7.418m	154.868ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	7.418m	154.868ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	7.418m	154.868ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	7.418m	154.868ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	7.418m	154.868ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	7.418m	154.868ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	26.820s	3.755ms	200	200	100.00
		otp_ctrl_sec_cm	7.418m	154.868ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	26.820s	3.755ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	26.820s	3.755ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	26.820s	3.755ms	200	200	100.00
		otp_ctrl_macro_errs	1.266m	24.559ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	26.820s	3.755ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	26.820s	3.755ms	200	200	100.00
		otp_ctrl_sec_cm	7.418m	154.868ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	26.820s	3.755ms	200	200	100.00
		otp_ctrl_sec_cm	7.418m	154.868ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	26.820s	3.755ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	26.820s	3.755ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	26.820s	3.755ms	200	200	100.00
		otp_ctrl_macro_errs	1.266m	24.559ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	26.820s	3.755ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	26.820s	3.755ms	200	200	100.00
		otp_ctrl_sec_cm	7.418m	154.868ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	7.970s	2.525ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.216m	15.000ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.030m	25.651ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.030m	25.651ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.030m	25.651ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.030m	25.651ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.030m	25.651ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	19.540s	16.502ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.030m	25.651ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	19.540s	16.502ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	7.418m	154.868ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	15.570s	4.676ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	19.540s	16.502ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	19.540s	16.502ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.266m	24.559ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	10.730s	3.047ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.205h	407.654ms	81	100	81.00
V3		TOTAL			82	101	81.19
		TOTAL			1324	1343	98.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.80	93.86	96.23	95.49	91.17	97.15	96.34	93.35

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 7 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 7 failures.
  - 7.otp_ctrl_stress_all_with_rand_reset.114172666780160697049989295063296136283181040261581635522499196921702823775959
    Line 15621, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9389616377 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 9389616377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.otp_ctrl_stress_all_with_rand_reset.105418404408039293454647302327738038110544567172499740868464152175153977079833
    Line 11704, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13013007564 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 13013007564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 6 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 6 failures.
  - 21.otp_ctrl_stress_all_with_rand_reset.74274381211534914600385840862606011974716773709888363200254977592565938221803
    Line 3360, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3797626330 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (320558621 [0x131b561d] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 3797626330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 26.otp_ctrl_stress_all_with_rand_reset.12353489309030911513164620694000250926360097604504792094164268223484737514049
    Line 33078, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17088327773 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2934868032 [0xaeee8840] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 17088327773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Offending '(cio_test_en_o == *)' has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 6.otp_ctrl_stress_all_with_rand_reset.92161011015606028030604736422364822471126507497584330099225049623769062731449
    Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 106846653 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 106846653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 39.otp_ctrl_stress_all_with_rand_reset.99779012606010260023448154252608040315139393310786355810664827794070822542657
    Line 27672, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 16275248155 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 16275248155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:839) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 44.otp_ctrl_stress_all_with_rand_reset.98339650955576701070378640323724723600228599339901970462924330657115379954307
    Line 14773, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20311247272 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 20311247272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 52.otp_ctrl_stress_all_with_rand_reset.107661392854003705944009855406266039159078936614619316969505919446513416722824
    Line 73171, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/52.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 186503395445 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 186503395445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 35.otp_ctrl_stress_all_with_rand_reset.81127960538224817690093954550971143928738910334188287416407192768450643100704
    Line 793, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13615569852 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 4207389078 [0xfac7a996]) dai addr 78c rdata0 readout mismatch
  UVM_INFO @ 13615569852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

37.otp_ctrl_stress_all_with_rand_reset.96722908039511973201232766821557093095797370135473199853517985009251783443221
Line 5706, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 2505626441 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 2506547501 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 2506652765 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 2507758037 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 2507994881 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1