OTP_CTRL Simulation Results

Sunday July 28 2024 23:02:28 UTC

GitHub Revision: `eca25c0ff8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 35694793988142953409419697382868702825984401131209466119932029294128690866559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.830s	101.217us	1	1	100.00
V1	smoke	otp_ctrl_smoke	17.670s	6.352ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	3.400s	1.009ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.030s	584.996us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	7.120s	926.157us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	8.310s	3.120ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.750s	1.724ms	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.030s	584.996us	20	20	100.00
		otp_ctrl_csr_aliasing	8.310s	3.120ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.860s	544.902us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.460s	84.338us	5	5	100.00
V1		TOTAL			114	116	98.28
V2	dai_access_partition_walk	otp_ctrl_partition_walk	20.320s	766.279us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	10.630s	3.048ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	1.193m	8.028ms	10	10	100.00
		otp_ctrl_check_fail	49.520s	20.975ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	18.630s	4.546ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	40.950s	4.216ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	56.480s	19.265ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	36.170s	13.209ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	46.720s	14.783ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	44.820s	13.005ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	58.330s	21.753ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	56.730s	15.106ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	9.005m	301.926ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	1.990s	552.184us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.980s	811.008us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	8.150s	678.717us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	8.150s	678.717us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	3.400s	1.009ms	5	5	100.00
		otp_ctrl_csr_rw	2.030s	584.996us	20	20	100.00
		otp_ctrl_csr_aliasing	8.310s	3.120ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.230s	1.937ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	3.400s	1.009ms	5	5	100.00
		otp_ctrl_csr_rw	2.030s	584.996us	20	20	100.00
		otp_ctrl_csr_aliasing	8.310s	3.120ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.230s	1.937ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.088m	173.021ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.088m	173.021ms	5	5	100.00
		otp_ctrl_tl_intg_err	37.790s	19.710ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.088m	173.021ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.088m	173.021ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	37.790s	19.710ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	17.670s	6.352ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	17.670s	6.352ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.088m	173.021ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.088m	173.021ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.088m	173.021ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.088m	173.021ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.088m	173.021ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.088m	173.021ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.088m	173.021ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.088m	173.021ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.088m	173.021ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.088m	173.021ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.088m	173.021ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.088m	173.021ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.088m	173.021ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.088m	173.021ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.088m	173.021ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	46.720s	14.783ms	200	200	100.00
		otp_ctrl_sec_cm	4.088m	173.021ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	46.720s	14.783ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	46.720s	14.783ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	46.720s	14.783ms	200	200	100.00
		otp_ctrl_macro_errs	58.330s	21.753ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	46.720s	14.783ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	46.720s	14.783ms	200	200	100.00
		otp_ctrl_sec_cm	4.088m	173.021ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	46.720s	14.783ms	200	200	100.00
		otp_ctrl_sec_cm	4.088m	173.021ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	46.720s	14.783ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	46.720s	14.783ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	46.720s	14.783ms	200	200	100.00
		otp_ctrl_macro_errs	58.330s	21.753ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	46.720s	14.783ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	46.720s	14.783ms	200	200	100.00
		otp_ctrl_sec_cm	4.088m	173.021ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	10.630s	3.048ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	49.520s	20.975ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	40.950s	4.216ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	40.950s	4.216ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	40.950s	4.216ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	40.950s	4.216ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	40.950s	4.216ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	17.670s	6.352ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	40.950s	4.216ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	17.670s	6.352ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.088m	173.021ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	18.630s	4.546ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	17.670s	6.352ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	17.670s	6.352ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	58.330s	21.753ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	18.480s	5.983ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.234h	1.846s	82	100	82.00
V3		TOTAL			83	101	82.18
		TOTAL			1323	1343	98.51

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.75	93.81	96.15	95.57	90.93	97.10	96.34	93.35

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 8 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 8 failures.
  - 0.otp_ctrl_stress_all_with_rand_reset.84709126990537743092816577906655101018715036482464110952451062360831614202287
    Line 13194, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 24307993965 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3646216511 [0xd954d93f] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 24307993965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.otp_ctrl_stress_all_with_rand_reset.18393543088253443876283069657580885990004799724405334987033647129812052330549
    Line 342, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  48121418 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1918090483 [0x7253bcf3] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @  48121418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 5 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 5 failures.
  - 13.otp_ctrl_stress_all_with_rand_reset.18839116025458091671367167609916219856968710946113137975014130425525057047048
    Line 8710, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1751765438 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 1751765438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.otp_ctrl_stress_all_with_rand_reset.107059935396397777686283258529982379610560268289045046273899750817916253235005
    Line 26918, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 200491364548 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 200491364548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
Offending '(cio_test_en_o == *)' has 4 failures:
- Test otp_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 6.otp_ctrl_csr_mem_rw_with_rand_reset.31865561585800751706315344353669428493989669894419378893506043732218764279209
    Line 267, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  37990944 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  37990944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 13.otp_ctrl_csr_mem_rw_with_rand_reset.13353439002745437760808850110637386015046226899229145997977926893985396459227
    Line 276, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 119027888 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 119027888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 15.otp_ctrl_stress_all_with_rand_reset.87084717565086349680406755275214200333571218917548890984090641122109369749918
    Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  27028803 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  27028803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 43.otp_ctrl_stress_all_with_rand_reset.26976162983761238662475247387182849109790458759679156961642379801187678569168
    Line 31334, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 137085784160 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 137085784160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:839) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 44.otp_ctrl_stress_all_with_rand_reset.16093597568332317515968321687672281902999717061397553358049423331144975864560
    Line 70177, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1134660565693 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1134660565693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ec rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 79.otp_ctrl_stress_all_with_rand_reset.827282019055117735151364674396704723280260107097749219928303575632753799495
    Line 50536, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/79.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 36285703841 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 492 [0x1ec]) dai addr 1ec rdata0 readout mismatch
  UVM_INFO @ 36285703841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

94.otp_ctrl_stress_all_with_rand_reset.40674185022949646589441943125652137904064621778485241136584878319030025012481
Line 22809, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/94.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 65669452335 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 65669990803 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 65670336961 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 65671375435 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 65671490821 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1