OTP_CTRL Simulation Results

Monday July 29 2024 23:02:32 UTC

GitHub Revision: `39f3866b56`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 91682663165753342493852681547271085771042321116470426223748766059309541455602

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.710s	51.324us	1	1	100.00
V1	smoke	otp_ctrl_smoke	36.110s	4.872ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.450s	118.628us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.140s	680.973us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	8.380s	359.849us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.560s	238.885us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.890s	1.719ms	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.140s	680.973us	20	20	100.00
		otp_ctrl_csr_aliasing	6.560s	238.885us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.850s	525.846us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.480s	538.693us	5	5	100.00
V1		TOTAL			115	116	99.14
V2	dai_access_partition_walk	otp_ctrl_partition_walk	21.600s	816.140us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	11.460s	3.714ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	41.580s	6.395ms	10	10	100.00
		otp_ctrl_check_fail	54.120s	23.230ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	13.620s	4.023ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	38.420s	15.038ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	38.520s	14.893ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	28.090s	9.583ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	29.500s	11.661ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	49.510s	17.063ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	57.890s	5.483ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	45.720s	2.195ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	10.270m	122.833ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.250s	617.238us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.680s	316.317us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	10.150s	3.064ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	10.150s	3.064ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.450s	118.628us	5	5	100.00
		otp_ctrl_csr_rw	2.140s	680.973us	20	20	100.00
		otp_ctrl_csr_aliasing	6.560s	238.885us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.290s	464.722us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.450s	118.628us	5	5	100.00
		otp_ctrl_csr_rw	2.140s	680.973us	20	20	100.00
		otp_ctrl_csr_aliasing	6.560s	238.885us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.290s	464.722us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	5.070m	165.040ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	5.070m	165.040ms	5	5	100.00
		otp_ctrl_tl_intg_err	38.300s	18.969ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	5.070m	165.040ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	5.070m	165.040ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	38.300s	18.969ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	36.110s	4.872ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	36.110s	4.872ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	5.070m	165.040ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	5.070m	165.040ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	5.070m	165.040ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	5.070m	165.040ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	5.070m	165.040ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	5.070m	165.040ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	5.070m	165.040ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	5.070m	165.040ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	5.070m	165.040ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	5.070m	165.040ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	5.070m	165.040ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	5.070m	165.040ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	5.070m	165.040ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	5.070m	165.040ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	5.070m	165.040ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	29.500s	11.661ms	200	200	100.00
		otp_ctrl_sec_cm	5.070m	165.040ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	29.500s	11.661ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	29.500s	11.661ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	29.500s	11.661ms	200	200	100.00
		otp_ctrl_macro_errs	57.890s	5.483ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	29.500s	11.661ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	29.500s	11.661ms	200	200	100.00
		otp_ctrl_sec_cm	5.070m	165.040ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	29.500s	11.661ms	200	200	100.00
		otp_ctrl_sec_cm	5.070m	165.040ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	29.500s	11.661ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	29.500s	11.661ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	29.500s	11.661ms	200	200	100.00
		otp_ctrl_macro_errs	57.890s	5.483ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	29.500s	11.661ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	29.500s	11.661ms	200	200	100.00
		otp_ctrl_sec_cm	5.070m	165.040ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	11.460s	3.714ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	54.120s	23.230ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	38.420s	15.038ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	38.420s	15.038ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	38.420s	15.038ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	38.420s	15.038ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	38.420s	15.038ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	36.110s	4.872ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	38.420s	15.038ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	36.110s	4.872ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	5.070m	165.040ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	13.620s	4.023ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	36.110s	4.872ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	36.110s	4.872ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	57.890s	5.483ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	17.540s	7.582ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.257h	337.015ms	85	100	85.00
V3		TOTAL			86	101	85.15
		TOTAL			1327	1343	98.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.93	93.76	96.67	96.09	91.17	97.19	96.34	93.28

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 7 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 7 failures.
  - 1.otp_ctrl_stress_all_with_rand_reset.20786878449404442220440178729581208297470776692643080262296885118496859176975
    Line 35805, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1240719718617 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 1240719718617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.otp_ctrl_stress_all_with_rand_reset.43215789549186332916665521854460159095287360620954977056035080135484278440970
    Line 56853, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 103037177365 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 103037177365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
Offending '(cio_test_en_o == *)' has 7 failures:
- Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 2.otp_ctrl_csr_mem_rw_with_rand_reset.77545004962578957354977846349832880230517960564684486324149224103342881261404
    Line 267, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 429241764 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 429241764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test otp_ctrl_stress_all_with_rand_reset has 6 failures.
  - 11.otp_ctrl_stress_all_with_rand_reset.29678178261617969820848929700863757478590941463837609351240089651182693911213
    Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  52309083 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  52309083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 20.otp_ctrl_stress_all_with_rand_reset.87050700354605993021310385114060389264805880064265385435856838880162055363486
    Line 9899, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 153444452679 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 153444452679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 4 more failures.

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

18.otp_ctrl_stress_all_with_rand_reset.43805571916091414169071184419189793741224334106210951925886373957165910726704
Line 1254, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 141123725 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 141154976 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 141165393 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 141436235 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 141488320 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 64.otp_ctrl_stress_all_with_rand_reset.39038952659402270207255571276372808737982201253006318172000028947903810067519
    Line 38063, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/64.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14979112527 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (704704720 [0x2a00f0d0] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 14979112527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```