OTP_CTRL Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: `fdfa12db04`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.740s	53.579us	1	1	100.00
V1	smoke	otp_ctrl_smoke	44.800s	5.426ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.790s	1.563ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.030s	544.700us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	6.350s	121.917us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	8.700s	3.148ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	5.460s	1.632ms	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.030s	544.700us	20	20	100.00
		otp_ctrl_csr_aliasing	8.700s	3.148ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.420s	133.785us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.630s	134.381us	5	5	100.00
V1		TOTAL			114	116	98.28
V2	dai_access_partition_walk	otp_ctrl_partition_walk	19.080s	611.416us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.510s	2.673ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	30.320s	4.398ms	10	10	100.00
		otp_ctrl_check_fail	42.570s	6.566ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	15.230s	4.191ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.604m	10.371ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	40.670s	1.354ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	31.830s	12.145ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	53.320s	14.768ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	52.930s	15.184ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	51.470s	5.066ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	2.151m	13.995ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	7.460m	31.916ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.060s	568.392us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.590s	734.408us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	6.920s	202.191us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	6.920s	202.191us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.790s	1.563ms	5	5	100.00
		otp_ctrl_csr_rw	2.030s	544.700us	20	20	100.00
		otp_ctrl_csr_aliasing	8.700s	3.148ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.250s	2.141ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.790s	1.563ms	5	5	100.00
		otp_ctrl_csr_rw	2.030s	544.700us	20	20	100.00
		otp_ctrl_csr_aliasing	8.700s	3.148ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.250s	2.141ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.447m	15.436ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.447m	15.436ms	5	5	100.00
		otp_ctrl_tl_intg_err	31.690s	18.909ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.447m	15.436ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.447m	15.436ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	31.690s	18.909ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	44.800s	5.426ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	44.800s	5.426ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.447m	15.436ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.447m	15.436ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.447m	15.436ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.447m	15.436ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.447m	15.436ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.447m	15.436ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.447m	15.436ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.447m	15.436ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.447m	15.436ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.447m	15.436ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.447m	15.436ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.447m	15.436ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.447m	15.436ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.447m	15.436ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.447m	15.436ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	53.320s	14.768ms	200	200	100.00
		otp_ctrl_sec_cm	3.447m	15.436ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	53.320s	14.768ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	53.320s	14.768ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	53.320s	14.768ms	200	200	100.00
		otp_ctrl_macro_errs	51.470s	5.066ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	53.320s	14.768ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	53.320s	14.768ms	200	200	100.00
		otp_ctrl_sec_cm	3.447m	15.436ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	53.320s	14.768ms	200	200	100.00
		otp_ctrl_sec_cm	3.447m	15.436ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	53.320s	14.768ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	53.320s	14.768ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	53.320s	14.768ms	200	200	100.00
		otp_ctrl_macro_errs	51.470s	5.066ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	53.320s	14.768ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	53.320s	14.768ms	200	200	100.00
		otp_ctrl_sec_cm	3.447m	15.436ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.510s	2.673ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	42.570s	6.566ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.604m	10.371ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.604m	10.371ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.604m	10.371ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.604m	10.371ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.604m	10.371ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	44.800s	5.426ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.604m	10.371ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	44.800s	5.426ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.447m	15.436ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	15.230s	4.191ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	44.800s	5.426ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	44.800s	5.426ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	51.470s	5.066ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	20.430s	7.279ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.140h	2.128s	89	100	89.00
V3		TOTAL			90	101	89.11
		TOTAL			1330	1343	99.03

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.77	93.79	96.18	95.84	90.93	97.05	96.34	93.28

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 5 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 5 failures.
  - 43.otp_ctrl_stress_all_with_rand_reset.2661113054386514305479977251500732103101124840182445448882136732326534803961
    Line 35957, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 42489491624 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 42489491624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 46.otp_ctrl_stress_all_with_rand_reset.71944837195654525471411644500781070201887988842009319602158569175266479253048
    Line 8111, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9486887022 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 9486887022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 3 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 3 failures.
  - 11.otp_ctrl_stress_all_with_rand_reset.95125986486135854522262335134663254448188117221931350229083499493172923372506
    Line 4070, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13195684373 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3018040522 [0xb3e3a4ca] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 13195684373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.otp_ctrl_stress_all_with_rand_reset.82152403306495303119758267765850847411017310241533569690034263287278968663649
    Line 93614, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 631753132505 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2376825970 [0x8dab7c72] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 631753132505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Offending '(cio_test_en_o == *)' has 2 failures:
- Test otp_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 3.otp_ctrl_csr_mem_rw_with_rand_reset.12961136794269610332100568889890517753187778704953797581983528001538657858658
    Line 276, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 978546377 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 978546377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 10.otp_ctrl_csr_mem_rw_with_rand_reset.29769263050049151358495732246313810646215853090389373870094461022006917604450
    Line 267, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  25872609 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  25872609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

21.otp_ctrl_stress_all_with_rand_reset.2420572276463816238227338131226566162652725177207945987523353434704852828064
Line 1286, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 21272198681 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 21272419271 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 21272433977 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 21272816333 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 21272831039 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 30.otp_ctrl_stress_all_with_rand_reset.73248104659401257562645061836501915137298771921577755900384283243577794590766
    Line 51494, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 98202574115 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 98202574115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1158) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 63.otp_ctrl_stress_all_with_rand_reset.68849817704142847069097366598903683812056959737556722235883787940034940914502
    Line 65667, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/63.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 299820971998 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=0x86b5010, Comparison=CompareOpEq, exp_data=0x0, call_count=1158)
  UVM_INFO @ 299820971998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```