OTP_CTRL Simulation Results

Wednesday July 31 2024 23:02:38 UTC

GitHub Revision: e9b7e615a7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25204348267605859133056659113100703417171299070132656462514712657132693373848

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.680s	98.251us	1	1	100.00
V1	smoke	otp_ctrl_smoke	16.560s	4.398ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	4.780s	1.580ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.680s	667.681us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	9.340s	424.890us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	8.930s	3.060ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	5.300s	1.584ms	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.680s	667.681us	20	20	100.00
		otp_ctrl_csr_aliasing	8.930s	3.060ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.500s	131.047us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.390s	140.052us	5	5	100.00
V1		TOTAL			115	116	99.14
V2	dai_access_partition_walk	otp_ctrl_partition_walk	23.170s	2.119ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.950s	2.354ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	42.710s	2.810ms	10	10	100.00
		otp_ctrl_check_fail	37.570s	1.788ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	13.380s	4.148ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	39.690s	2.303ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.055m	31.474ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	36.730s	14.436ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	32.030s	17.413ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	55.140s	25.659ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.084m	7.744ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	50.490s	21.275ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	8.331m	113.975ms	49	50	98.00
V2	intr_test	otp_ctrl_intr_test	1.860s	578.273us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.030s	791.396us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	8.600s	2.869ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	8.600s	2.869ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	4.780s	1.580ms	5	5	100.00
		otp_ctrl_csr_rw	2.680s	667.681us	20	20	100.00
		otp_ctrl_csr_aliasing	8.930s	3.060ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.590s	2.046ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	4.780s	1.580ms	5	5	100.00
		otp_ctrl_csr_rw	2.680s	667.681us	20	20	100.00
		otp_ctrl_csr_aliasing	8.930s	3.060ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.590s	2.046ms	20	20	100.00
V2		TOTAL			1100	1101	99.91
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.774m	154.788ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.774m	154.788ms	5	5	100.00
		otp_ctrl_tl_intg_err	22.050s	2.037ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.774m	154.788ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.774m	154.788ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	22.050s	2.037ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	16.560s	4.398ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	16.560s	4.398ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.774m	154.788ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.774m	154.788ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.774m	154.788ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.774m	154.788ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.774m	154.788ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.774m	154.788ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.774m	154.788ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.774m	154.788ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.774m	154.788ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.774m	154.788ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.774m	154.788ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.774m	154.788ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.774m	154.788ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.774m	154.788ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.774m	154.788ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.030s	17.413ms	200	200	100.00
		otp_ctrl_sec_cm	4.774m	154.788ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.030s	17.413ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.030s	17.413ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.030s	17.413ms	200	200	100.00
		otp_ctrl_macro_errs	1.084m	7.744ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.030s	17.413ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.030s	17.413ms	200	200	100.00
		otp_ctrl_sec_cm	4.774m	154.788ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.030s	17.413ms	200	200	100.00
		otp_ctrl_sec_cm	4.774m	154.788ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.030s	17.413ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.030s	17.413ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.030s	17.413ms	200	200	100.00
		otp_ctrl_macro_errs	1.084m	7.744ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.030s	17.413ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.030s	17.413ms	200	200	100.00
		otp_ctrl_sec_cm	4.774m	154.788ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.950s	2.354ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	37.570s	1.788ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	39.690s	2.303ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	39.690s	2.303ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	39.690s	2.303ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	39.690s	2.303ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	39.690s	2.303ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	16.560s	4.398ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	39.690s	2.303ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	16.560s	4.398ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.774m	154.788ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	13.380s	4.148ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	16.560s	4.398ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	16.560s	4.398ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.084m	7.744ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.490s	5.929ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.272h	206.127ms	83	100	83.00
V3		TOTAL			84	101	83.17
		TOTAL			1324	1343	98.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.91	93.73	96.70	95.85	91.17	97.19	96.34	93.35

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 9 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 9 failures.

    • 5.otp_ctrl_stress_all_with_rand_reset.2264297513077325260615976595318165246198484879554524343779913979055249640424
      Line 15848, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 107224571042 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 107224571042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 8.otp_ctrl_stress_all_with_rand_reset.70612338598636772496441711100363088231419768511036758702521240956716579003572
      Line 35689, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 35564974805 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 35564974805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 7 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 5 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 5 failures.

    • 19.otp_ctrl_stress_all_with_rand_reset.5050007672543748331825438010000233167963835425361025266831653922715249427678
      Line 16739, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 71976776707 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1389734259 [0x52d5a973] vs 1913289495 [0x720a7b17]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 71976776707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 50.otp_ctrl_stress_all_with_rand_reset.42799847551256415743001384741986712591018456138673430205793691822935103935328
      Line 79539, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/50.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 535848145419 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1662530244 [0x631832c4] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 535848145419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

• Offending '(cio_test_en_o == *)' has 2 failures:

  • Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 14.otp_ctrl_csr_mem_rw_with_rand_reset.90521117518412249863734386957217691731296131887149091503755933435643895789921
      Line 276, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 247136431 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 247136431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 57.otp_ctrl_stress_all_with_rand_reset.39327452855922442675827702946779260794231725708942452550602449685109027109825
      Line 11862, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/57.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 12120107972 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 12120107972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 9.otp_ctrl_stress_all_with_rand_reset.98184271771888921150468813009047555263784770789208422364584707427375402149791
      Line 31606, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 191652055621 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 2090860013 [0x7c9ffded]) dai addr 750 rdata0 readout mismatch
        UVM_INFO @ 191652055621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:925) [scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (* [*] vs * [*]) reg name: status, compare_mask * has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 30.otp_ctrl_stress_all_with_rand_reset.652570146729589421791655108477524171299067369450566287372431293276550237041
      Line 88747, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 22997215000 ps: (otp_ctrl_scoreboard.sv:925) [uvm_test_top.env.scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (262175 [0x4001f] vs 262171 [0x4001b]) reg name: status, compare_mask 0
        UVM_INFO @ 22997215000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:608) [scoreboard] Check failed item.d_data == otp_a[otp_addr] (* [*] vs * [*]) mem read mismatch at TLUL addr *a8c6e*, csr_addr * has 1 failures:

  • Test otp_ctrl_stress_all has 1 failures.

    • 45.otp_ctrl_stress_all.112103770665653136932631360214521506885505975437946046815830256390468946502714
      Line 3218, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 111726559 ps: (otp_ctrl_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed item.d_data == otp_a[otp_addr] (4023907679 [0xefd7f55f] vs 701985092 [0x29d77144]) mem read mismatch at TLUL addr 6a8c6e70, csr_addr 670
        UVM_INFO @ 111726559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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