OTP_CTRL Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: 625f353e9c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.720s	180.596us	1	1	100.00
V1	smoke	otp_ctrl_smoke	22.330s	5.570ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.490s	1.034ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.090s	676.332us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	19.130s	6.791ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.090s	287.177us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.780s	1.657ms	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.090s	676.332us	20	20	100.00
		otp_ctrl_csr_aliasing	6.090s	287.177us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.480s	528.496us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.430s	38.058us	5	5	100.00
V1		TOTAL			115	116	99.14
V2	dai_access_partition_walk	otp_ctrl_partition_walk	22.430s	2.396ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.510s	2.430ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	50.730s	2.577ms	10	10	100.00
		otp_ctrl_check_fail	1.070m	6.574ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	13.480s	671.527us	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.171m	8.403ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	52.400s	3.664ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	41.230s	12.773ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	36.040s	13.246ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	49.390s	15.048ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.676m	12.112ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	46.190s	9.335ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	8.475m	36.305ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	1.960s	515.117us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.620s	475.221us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.430s	176.957us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.430s	176.957us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.490s	1.034ms	5	5	100.00
		otp_ctrl_csr_rw	2.090s	676.332us	20	20	100.00
		otp_ctrl_csr_aliasing	6.090s	287.177us	5	5	100.00
		otp_ctrl_same_csr_outstanding	6.750s	1.851ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.490s	1.034ms	5	5	100.00
		otp_ctrl_csr_rw	2.090s	676.332us	20	20	100.00
		otp_ctrl_csr_aliasing	6.090s	287.177us	5	5	100.00
		otp_ctrl_same_csr_outstanding	6.750s	1.851ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.495m	37.136ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.495m	37.136ms	5	5	100.00
		otp_ctrl_tl_intg_err	44.750s	18.814ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.495m	37.136ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.495m	37.136ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	44.750s	18.814ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	22.330s	5.570ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	22.330s	5.570ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.495m	37.136ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.495m	37.136ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.495m	37.136ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.495m	37.136ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.495m	37.136ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.495m	37.136ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.495m	37.136ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.495m	37.136ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.495m	37.136ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.495m	37.136ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.495m	37.136ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.495m	37.136ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.495m	37.136ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.495m	37.136ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.495m	37.136ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.040s	13.246ms	200	200	100.00
		otp_ctrl_sec_cm	3.495m	37.136ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.040s	13.246ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.040s	13.246ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.040s	13.246ms	200	200	100.00
		otp_ctrl_macro_errs	1.676m	12.112ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.040s	13.246ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.040s	13.246ms	200	200	100.00
		otp_ctrl_sec_cm	3.495m	37.136ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.040s	13.246ms	200	200	100.00
		otp_ctrl_sec_cm	3.495m	37.136ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.040s	13.246ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.040s	13.246ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.040s	13.246ms	200	200	100.00
		otp_ctrl_macro_errs	1.676m	12.112ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.040s	13.246ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.040s	13.246ms	200	200	100.00
		otp_ctrl_sec_cm	3.495m	37.136ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.510s	2.430ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.070m	6.574ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.171m	8.403ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.171m	8.403ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.171m	8.403ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.171m	8.403ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.171m	8.403ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	22.330s	5.570ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.171m	8.403ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	22.330s	5.570ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.495m	37.136ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	13.480s	671.527us	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	22.330s	5.570ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	22.330s	5.570ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.676m	12.112ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	11.450s	6.976ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.471h	2.524s	77	100	77.00
V3		TOTAL			78	101	77.23
		TOTAL			1319	1343	98.21

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.86	93.81	96.18	95.65	91.65	97.10	96.34	93.28

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 10 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 10 failures.

    • 6.otp_ctrl_stress_all_with_rand_reset.37812348247190232815663611005313580215501072610023068270102963349238351402632
      Line 44147, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 121137897740 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 121137897740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 20.otp_ctrl_stress_all_with_rand_reset.96146998885280224347949943363191341224797315371987674737472042232685988030776
      Line 97280, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 313013900324 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 313013900324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 8 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 7 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 7 failures.

    • 9.otp_ctrl_stress_all_with_rand_reset.99128880216020387205868557313005933837168673369637379511537778070899897569876
      Line 4314, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 136400278282 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (406716928 [0x183e0200] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 136400278282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 32.otp_ctrl_stress_all_with_rand_reset.39182518718964988023465376059631135226744600936887785401586282792883779844667
      Line 7777, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 347789333945 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3585155209 [0xd5b12089] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 347789333945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• Offending '(cio_test_en_o == *)' has 3 failures:

  • Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 7.otp_ctrl_csr_mem_rw_with_rand_reset.19034334780992078195043776731248662477937091887998100278361729412042325426673
      Line 267, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @  36390051 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @  36390051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

    • 23.otp_ctrl_stress_all_with_rand_reset.35745779818083673815614104147728277222347123753424353520587916594114330159405
      Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @  26320252 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @  26320252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 60.otp_ctrl_stress_all_with_rand_reset.71160856983420115928389571461515105471777049928902779330632036544226700978647
      Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/60.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @  53671560 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @  53671560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 7.otp_ctrl_stress_all_with_rand_reset.38453161157712993955460016767463144304762939763383879809417638584931245877027
      Line 64528, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 29775782163 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0
        UVM_INFO @ 29775782163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *f* rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 33.otp_ctrl_stress_all_with_rand_reset.76718058326348210093390008386035736988627385918140911847244996810646915077659
      Line 271, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3933407436 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1776 [0x6f0]) dai addr 6f0 rdata0 readout mismatch
        UVM_INFO @ 3933407436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 52.otp_ctrl_stress_all_with_rand_reset.17071808408761929498946538741362080928202473090802695583348004667534183789633
      Line 10396, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/52.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 54381200671 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 3322379679 [0xc6077d9f]) dai addr 780 rdata0 readout mismatch
        UVM_INFO @ 54381200671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr e* rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 98.otp_ctrl_stress_all_with_rand_reset.88270949443139508354354391790633135620742097083028582728017324734083327820590
      Line 23541, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/98.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12254057811 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 228 [0xe4]) dai addr e4 rdata0 readout mismatch
        UVM_INFO @ 12254057811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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• 2024.08.01_09.38.25
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• 2024.07.30_09.25.16
• 2024.07.29_07.50.10
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