OTP_CTRL Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: 625f353e9c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 wake_up otp_ctrl_wake_up 1.720s 180.596us 1 1 100.00
V1 smoke otp_ctrl_smoke 22.330s 5.570ms 50 50 100.00
V1 csr_hw_reset otp_ctrl_csr_hw_reset 2.490s 1.034ms 5 5 100.00
V1 csr_rw otp_ctrl_csr_rw 2.090s 676.332us 20 20 100.00
V1 csr_bit_bash otp_ctrl_csr_bit_bash 19.130s 6.791ms 5 5 100.00
V1 csr_aliasing otp_ctrl_csr_aliasing 6.090s 287.177us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otp_ctrl_csr_mem_rw_with_rand_reset 4.780s 1.657ms 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr otp_ctrl_csr_rw 2.090s 676.332us 20 20 100.00
otp_ctrl_csr_aliasing 6.090s 287.177us 5 5 100.00
V1 mem_walk otp_ctrl_mem_walk 1.480s 528.496us 5 5 100.00
V1 mem_partial_access otp_ctrl_mem_partial_access 1.430s 38.058us 5 5 100.00
V1 TOTAL 115 116 99.14
V2 dai_access_partition_walk otp_ctrl_partition_walk 22.430s 2.396ms 1 1 100.00
V2 init_fail otp_ctrl_init_fail 8.510s 2.430ms 300 300 100.00
V2 partition_check otp_ctrl_background_chks 50.730s 2.577ms 10 10 100.00
otp_ctrl_check_fail 1.070m 6.574ms 50 50 100.00
V2 regwen_during_otp_init otp_ctrl_regwen 13.480s 671.527us 50 50 100.00
V2 partition_lock otp_ctrl_dai_lock 1.171m 8.403ms 50 50 100.00
V2 interface_key_check otp_ctrl_parallel_key_req 52.400s 3.664ms 50 50 100.00
V2 lc_interactions otp_ctrl_parallel_lc_req 41.230s 12.773ms 50 50 100.00
otp_ctrl_parallel_lc_esc 36.040s 13.246ms 200 200 100.00
V2 otp_dai_errors otp_ctrl_dai_errs 49.390s 15.048ms 50 50 100.00
V2 otp_macro_errors otp_ctrl_macro_errs 1.676m 12.112ms 50 50 100.00
V2 test_access otp_ctrl_test_access 46.190s 9.335ms 50 50 100.00
V2 stress_all otp_ctrl_stress_all 8.475m 36.305ms 50 50 100.00
V2 intr_test otp_ctrl_intr_test 1.960s 515.117us 50 50 100.00
V2 alert_test otp_ctrl_alert_test 3.620s 475.221us 50 50 100.00
V2 tl_d_oob_addr_access otp_ctrl_tl_errors 7.430s 176.957us 20 20 100.00
V2 tl_d_illegal_access otp_ctrl_tl_errors 7.430s 176.957us 20 20 100.00
V2 tl_d_outstanding_access otp_ctrl_csr_hw_reset 2.490s 1.034ms 5 5 100.00
otp_ctrl_csr_rw 2.090s 676.332us 20 20 100.00
otp_ctrl_csr_aliasing 6.090s 287.177us 5 5 100.00
otp_ctrl_same_csr_outstanding 6.750s 1.851ms 20 20 100.00
V2 tl_d_partial_access otp_ctrl_csr_hw_reset 2.490s 1.034ms 5 5 100.00
otp_ctrl_csr_rw 2.090s 676.332us 20 20 100.00
otp_ctrl_csr_aliasing 6.090s 287.177us 5 5 100.00
otp_ctrl_same_csr_outstanding 6.750s 1.851ms 20 20 100.00
V2 TOTAL 1101 1101 100.00
V2S sec_cm_additional_check otp_ctrl_sec_cm 3.495m 37.136ms 5 5 100.00
V2S tl_intg_err otp_ctrl_sec_cm 3.495m 37.136ms 5 5 100.00
otp_ctrl_tl_intg_err 44.750s 18.814ms 20 20 100.00
V2S prim_count_check otp_ctrl_sec_cm 3.495m 37.136ms 5 5 100.00
V2S prim_fsm_check otp_ctrl_sec_cm 3.495m 37.136ms 5 5 100.00
V2S sec_cm_bus_integrity otp_ctrl_tl_intg_err 44.750s 18.814ms 20 20 100.00
V2S sec_cm_secret_mem_scramble otp_ctrl_smoke 22.330s 5.570ms 50 50 100.00
V2S sec_cm_part_mem_digest otp_ctrl_smoke 22.330s 5.570ms 50 50 100.00
V2S sec_cm_dai_fsm_sparse otp_ctrl_sec_cm 3.495m 37.136ms 5 5 100.00
V2S sec_cm_kdi_fsm_sparse otp_ctrl_sec_cm 3.495m 37.136ms 5 5 100.00
V2S sec_cm_lci_fsm_sparse otp_ctrl_sec_cm 3.495m 37.136ms 5 5 100.00
V2S sec_cm_part_fsm_sparse otp_ctrl_sec_cm 3.495m 37.136ms 5 5 100.00
V2S sec_cm_scrmbl_fsm_sparse otp_ctrl_sec_cm 3.495m 37.136ms 5 5 100.00
V2S sec_cm_timer_fsm_sparse otp_ctrl_sec_cm 3.495m 37.136ms 5 5 100.00
V2S sec_cm_dai_ctr_redun otp_ctrl_sec_cm 3.495m 37.136ms 5 5 100.00
V2S sec_cm_kdi_seed_ctr_redun otp_ctrl_sec_cm 3.495m 37.136ms 5 5 100.00
V2S sec_cm_kdi_entropy_ctr_redun otp_ctrl_sec_cm 3.495m 37.136ms 5 5 100.00
V2S sec_cm_lci_ctr_redun otp_ctrl_sec_cm 3.495m 37.136ms 5 5 100.00
V2S sec_cm_part_ctr_redun otp_ctrl_sec_cm 3.495m 37.136ms 5 5 100.00
V2S sec_cm_scrmbl_ctr_redun otp_ctrl_sec_cm 3.495m 37.136ms 5 5 100.00
V2S sec_cm_timer_integ_ctr_redun otp_ctrl_sec_cm 3.495m 37.136ms 5 5 100.00
V2S sec_cm_timer_cnsty_ctr_redun otp_ctrl_sec_cm 3.495m 37.136ms 5 5 100.00
V2S sec_cm_timer_lfsr_redun otp_ctrl_sec_cm 3.495m 37.136ms 5 5 100.00
V2S sec_cm_dai_fsm_local_esc otp_ctrl_parallel_lc_esc 36.040s 13.246ms 200 200 100.00
otp_ctrl_sec_cm 3.495m 37.136ms 5 5 100.00
V2S sec_cm_lci_fsm_local_esc otp_ctrl_parallel_lc_esc 36.040s 13.246ms 200 200 100.00
V2S sec_cm_kdi_fsm_local_esc otp_ctrl_parallel_lc_esc 36.040s 13.246ms 200 200 100.00
V2S sec_cm_part_fsm_local_esc otp_ctrl_parallel_lc_esc 36.040s 13.246ms 200 200 100.00
otp_ctrl_macro_errs 1.676m 12.112ms 50 50 100.00
V2S sec_cm_scrmbl_fsm_local_esc otp_ctrl_parallel_lc_esc 36.040s 13.246ms 200 200 100.00
V2S sec_cm_timer_fsm_local_esc otp_ctrl_parallel_lc_esc 36.040s 13.246ms 200 200 100.00
otp_ctrl_sec_cm 3.495m 37.136ms 5 5 100.00
V2S sec_cm_dai_fsm_global_esc otp_ctrl_parallel_lc_esc 36.040s 13.246ms 200 200 100.00
otp_ctrl_sec_cm 3.495m 37.136ms 5 5 100.00
V2S sec_cm_lci_fsm_global_esc otp_ctrl_parallel_lc_esc 36.040s 13.246ms 200 200 100.00
V2S sec_cm_kdi_fsm_global_esc otp_ctrl_parallel_lc_esc 36.040s 13.246ms 200 200 100.00
V2S sec_cm_part_fsm_global_esc otp_ctrl_parallel_lc_esc 36.040s 13.246ms 200 200 100.00
otp_ctrl_macro_errs 1.676m 12.112ms 50 50 100.00
V2S sec_cm_scrmbl_fsm_global_esc otp_ctrl_parallel_lc_esc 36.040s 13.246ms 200 200 100.00
V2S sec_cm_timer_fsm_global_esc otp_ctrl_parallel_lc_esc 36.040s 13.246ms 200 200 100.00
otp_ctrl_sec_cm 3.495m 37.136ms 5 5 100.00
V2S sec_cm_part_data_reg_integrity otp_ctrl_init_fail 8.510s 2.430ms 300 300 100.00
V2S sec_cm_part_data_reg_bkgn_chk otp_ctrl_check_fail 1.070m 6.574ms 50 50 100.00
V2S sec_cm_part_mem_regren otp_ctrl_dai_lock 1.171m 8.403ms 50 50 100.00
V2S sec_cm_part_mem_sw_unreadable otp_ctrl_dai_lock 1.171m 8.403ms 50 50 100.00
V2S sec_cm_part_mem_sw_unwritable otp_ctrl_dai_lock 1.171m 8.403ms 50 50 100.00
V2S sec_cm_lc_part_mem_sw_noaccess otp_ctrl_dai_lock 1.171m 8.403ms 50 50 100.00
V2S sec_cm_access_ctrl_mubi otp_ctrl_dai_lock 1.171m 8.403ms 50 50 100.00
V2S sec_cm_token_valid_ctrl_mubi otp_ctrl_smoke 22.330s 5.570ms 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi otp_ctrl_dai_lock 1.171m 8.403ms 50 50 100.00
V2S sec_cm_test_bus_lc_gated otp_ctrl_smoke 22.330s 5.570ms 50 50 100.00
V2S sec_cm_test_tl_lc_gate_fsm_sparse otp_ctrl_sec_cm 3.495m 37.136ms 5 5 100.00
V2S sec_cm_direct_access_config_regwen otp_ctrl_regwen 13.480s 671.527us 50 50 100.00
V2S sec_cm_check_trigger_config_regwen otp_ctrl_smoke 22.330s 5.570ms 50 50 100.00
V2S sec_cm_check_config_regwen otp_ctrl_smoke 22.330s 5.570ms 50 50 100.00
V2S sec_cm_macro_mem_integrity otp_ctrl_macro_errs 1.676m 12.112ms 50 50 100.00
V2S TOTAL 25 25 100.00
V3 otp_ctrl_low_freq_read otp_ctrl_low_freq_read 11.450s 6.976ms 1 1 100.00
V3 stress_all_with_rand_reset otp_ctrl_stress_all_with_rand_reset 1.471h 2.524s 77 100 77.00
V3 TOTAL 78 101 77.23
TOTAL 1319 1343 98.21

Testplan Progress

Items Total Written Passing Progress
V1 9 9 8 88.89
V2 17 17 17 100.00
V2S 2 2 2 100.00
V3 2 2 1 50.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.86 93.81 96.18 95.65 91.65 97.10 96.34 93.28

Failure Buckets

Past Results