OTP_CTRL Simulation Results

Friday August 02 2024 23:02:48 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 75989420798843487383163268541581889763599806834398027919895759109584083292465

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.760s	103.573us	1	1	100.00
V1	smoke	otp_ctrl_smoke	12.960s	793.004us	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.780s	1.579ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.050s	659.979us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	7.130s	3.762ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.820s	1.232ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	5.760s	1.640ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.050s	659.979us	20	20	100.00
		otp_ctrl_csr_aliasing	6.820s	1.232ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.450s	77.328us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.620s	544.720us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	20.850s	613.576us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.710s	2.591ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	25.620s	2.585ms	10	10	100.00
		otp_ctrl_check_fail	56.840s	21.466ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	16.550s	4.135ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.486m	34.273ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	40.930s	1.579ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	27.510s	785.155us	50	50	100.00
		otp_ctrl_parallel_lc_esc	39.670s	13.259ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.001m	23.611ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.179m	24.677ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.599m	11.271ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	16.116m	95.150ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.080s	539.808us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	4.040s	321.266us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.390s	202.712us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.390s	202.712us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.780s	1.579ms	5	5	100.00
		otp_ctrl_csr_rw	2.050s	659.979us	20	20	100.00
		otp_ctrl_csr_aliasing	6.820s	1.232ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.230s	1.721ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.780s	1.579ms	5	5	100.00
		otp_ctrl_csr_rw	2.050s	659.979us	20	20	100.00
		otp_ctrl_csr_aliasing	6.820s	1.232ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.230s	1.721ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.464m	154.668ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.464m	154.668ms	5	5	100.00
		otp_ctrl_tl_intg_err	28.990s	20.206ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.464m	154.668ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.464m	154.668ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	28.990s	20.206ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	12.960s	793.004us	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	12.960s	793.004us	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.464m	154.668ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.464m	154.668ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.464m	154.668ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.464m	154.668ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.464m	154.668ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.464m	154.668ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.464m	154.668ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.464m	154.668ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.464m	154.668ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.464m	154.668ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.464m	154.668ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.464m	154.668ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.464m	154.668ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.464m	154.668ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.464m	154.668ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.670s	13.259ms	200	200	100.00
		otp_ctrl_sec_cm	4.464m	154.668ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.670s	13.259ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.670s	13.259ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.670s	13.259ms	200	200	100.00
		otp_ctrl_macro_errs	1.179m	24.677ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.670s	13.259ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.670s	13.259ms	200	200	100.00
		otp_ctrl_sec_cm	4.464m	154.668ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.670s	13.259ms	200	200	100.00
		otp_ctrl_sec_cm	4.464m	154.668ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.670s	13.259ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.670s	13.259ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.670s	13.259ms	200	200	100.00
		otp_ctrl_macro_errs	1.179m	24.677ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.670s	13.259ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.670s	13.259ms	200	200	100.00
		otp_ctrl_sec_cm	4.464m	154.668ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.710s	2.591ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	56.840s	21.466ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.486m	34.273ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.486m	34.273ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.486m	34.273ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.486m	34.273ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.486m	34.273ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	12.960s	793.004us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.486m	34.273ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	12.960s	793.004us	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.464m	154.668ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	16.550s	4.135ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	12.960s	793.004us	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	12.960s	793.004us	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.179m	24.677ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	19.690s	5.925ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.103h	1.084s	82	100	82.00
V3		TOTAL			83	101	82.18
		TOTAL			1325	1343	98.66

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.95	93.81	96.18	95.56	92.36	97.10	96.34	93.28

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 8 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 8 failures.
  - 20.otp_ctrl_stress_all_with_rand_reset.10060483746479466294583011224751594098097130191455849998020220582224532605980
    Line 319, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  34253320 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @  34253320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.otp_ctrl_stress_all_with_rand_reset.12295388835976543667851419374187961101798622026746131395747266018836932113919
    Line 43368, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 28268764151 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 28268764151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 4 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 4 failures.
  - 5.otp_ctrl_stress_all_with_rand_reset.7443358065689433677317200617278419887551237762061654018738950067282653925515
    Line 51315, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 474666454442 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2021395069 [0x787c0a7d] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 474666454442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.otp_ctrl_stress_all_with_rand_reset.79772742006459000214604586171320128357959227464953050838975701695770219911599
    Line 2187, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 166942304361 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2274316614 [0x878f5146] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 166942304361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 30.otp_ctrl_stress_all_with_rand_reset.114552950731108573009175910108722056239843021676577064762417044117119473029946
    Line 42926, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 141598044520 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0
  UVM_INFO @ 141598044520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 64.otp_ctrl_stress_all_with_rand_reset.84047251550369514127519911004039715926439559061981155892624253570124344078179
    Line 3211, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/64.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3329316093 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0
  UVM_INFO @ 3329316093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

16.otp_ctrl_stress_all_with_rand_reset.65295441556250927521320776686310564594470747322375673368720355221591849434840
Line 10761, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 299236726972 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 299237060306 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 299498894163 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 299500227499 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 299501727502 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (cip_base_vseq.sv:836) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 58.otp_ctrl_stress_all_with_rand_reset.45186911629328592971280759250081836854592567715821301769177759189049384275190
    Line 782423, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/58.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 299103942521 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 299103942521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1776) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 66.otp_ctrl_stress_all_with_rand_reset.104185819567386853109411414862807717256127998458731009650368642723146642615595
    Line 78558, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/66.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 709344839779 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=0xddf5e010, Comparison=CompareOpEq, exp_data=0x0, call_count=1776)
  UVM_INFO @ 709344839779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=603) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 74.otp_ctrl_stress_all_with_rand_reset.70638533938146376937712817522136557254363437188628984562488195130194726783618
    Line 90274, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/74.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 144755768706 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=0xc0ebd010, Comparison=CompareOpEq, exp_data=0x0, call_count=603)
  UVM_INFO @ 144755768706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```