OTP_CTRL Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.880s	131.411us	1	1	100.00
V1	smoke	otp_ctrl_smoke	20.570s	10.304ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	4.300s	1.550ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.220s	519.152us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	10.390s	3.733ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	7.870s	3.149ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	5.210s	1.701ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.220s	519.152us	20	20	100.00
		otp_ctrl_csr_aliasing	7.870s	3.149ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.850s	541.223us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.500s	140.087us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	18.330s	402.106us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	7.680s	2.403ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	37.770s	28.602ms	10	10	100.00
		otp_ctrl_check_fail	44.310s	4.338ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	16.130s	4.470ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	46.990s	16.108ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	52.200s	6.661ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	36.740s	10.713ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	49.880s	15.082ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.088m	22.227ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.029m	19.321ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.377m	8.608ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	16.366m	109.941ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.150s	596.372us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.560s	505.906us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	9.780s	3.382ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	9.780s	3.382ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	4.300s	1.550ms	5	5	100.00
		otp_ctrl_csr_rw	2.220s	519.152us	20	20	100.00
		otp_ctrl_csr_aliasing	7.870s	3.149ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.620s	224.156us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	4.300s	1.550ms	5	5	100.00
		otp_ctrl_csr_rw	2.220s	519.152us	20	20	100.00
		otp_ctrl_csr_aliasing	7.870s	3.149ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.620s	224.156us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	5.428m	169.813ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	5.428m	169.813ms	5	5	100.00
		otp_ctrl_tl_intg_err	43.160s	5.929ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	5.428m	169.813ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	5.428m	169.813ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	43.160s	5.929ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	20.570s	10.304ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	20.570s	10.304ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	5.428m	169.813ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	5.428m	169.813ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	5.428m	169.813ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	5.428m	169.813ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	5.428m	169.813ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	5.428m	169.813ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	5.428m	169.813ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	5.428m	169.813ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	5.428m	169.813ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	5.428m	169.813ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	5.428m	169.813ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	5.428m	169.813ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	5.428m	169.813ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	5.428m	169.813ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	5.428m	169.813ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	49.880s	15.082ms	200	200	100.00
		otp_ctrl_sec_cm	5.428m	169.813ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	49.880s	15.082ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	49.880s	15.082ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	49.880s	15.082ms	200	200	100.00
		otp_ctrl_macro_errs	1.029m	19.321ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	49.880s	15.082ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	49.880s	15.082ms	200	200	100.00
		otp_ctrl_sec_cm	5.428m	169.813ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	49.880s	15.082ms	200	200	100.00
		otp_ctrl_sec_cm	5.428m	169.813ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	49.880s	15.082ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	49.880s	15.082ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	49.880s	15.082ms	200	200	100.00
		otp_ctrl_macro_errs	1.029m	19.321ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	49.880s	15.082ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	49.880s	15.082ms	200	200	100.00
		otp_ctrl_sec_cm	5.428m	169.813ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	7.680s	2.403ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	44.310s	4.338ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	46.990s	16.108ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	46.990s	16.108ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	46.990s	16.108ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	46.990s	16.108ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	46.990s	16.108ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	20.570s	10.304ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	46.990s	16.108ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	20.570s	10.304ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	5.428m	169.813ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	16.130s	4.470ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	20.570s	10.304ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	20.570s	10.304ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.029m	19.321ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	14.960s	7.273ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.132h	1.887s	80	100	80.00
V3		TOTAL			81	101	80.20
		TOTAL			1323	1343	98.51

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.96	93.79	96.72	95.91	91.65	97.19	96.34	93.14

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 8 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 8 failures.
  - 5.otp_ctrl_stress_all_with_rand_reset.112422027752549820995043655571245074952819699789887633462103959151664090475358
    Line 14108, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 31796164799 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4202894963 [0xfa831673] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 31796164799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.otp_ctrl_stress_all_with_rand_reset.24318933310552893562662460372613516869493427946192567512167710429163805041933
    Line 12363, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 38546064399 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3170190731 [0xbcf5458b] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 38546064399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 5 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 5 failures.
  - 18.otp_ctrl_stress_all_with_rand_reset.108971886022933671736617610030350571387468276280705726214164469807796144344655
    Line 8514, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 27647724532 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 27647724532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.otp_ctrl_stress_all_with_rand_reset.23516661092697515805583601291107468511708260696290609549945167164892201165723
    Line 6504, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11675488699 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 11675488699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
Offending '(cio_test_en_o == *)' has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 35.otp_ctrl_stress_all_with_rand_reset.115572620781153689310496209030796892808830984124577209080707591818763705597596
    Line 7579, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 11255629079 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 11255629079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 71.otp_ctrl_stress_all_with_rand_reset.35893644923038845303856318817894602185213853997440273986515854456094742838228
    Line 34035, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/71.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 578822416500 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 578822416500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:836) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 37.otp_ctrl_stress_all_with_rand_reset.82200760385441248148207402423300866842286678104277260050702046459349854707662
    Line 51940, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 107921992044 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 107921992044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 79.otp_ctrl_stress_all_with_rand_reset.32781481914035715379497854691178145523357566413309605697960823336032764862122
    Line 157644, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/79.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 458269077580 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 458269077580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 15.otp_ctrl_stress_all_with_rand_reset.593859541815370184074374891839514116706741983569587994223947630135958823617
    Line 75992, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1160538181691 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 1160538181691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *b* rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 41.otp_ctrl_stress_all_with_rand_reset.8464801332891763686624722009031871738710399391876105567114227746707552792829
    Line 24003, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 78048537990 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 952 [0x3b8]) dai addr 3b8 rdata0 readout mismatch
  UVM_INFO @ 78048537990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 57.otp_ctrl_stress_all_with_rand_reset.81848974271353283636563536641044572332469181936594015613983163385681027243605
    Line 16824, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/57.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 252796410773 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0
  UVM_INFO @ 252796410773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

OTP_CTRL Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c8985d6745`