OTP_CTRL Simulation Results

Sunday August 04 2024 23:02:21 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107130591329296133632864610148388701578652631018704528920799220771546870921898

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	2.150s	193.325us	1	1	100.00
V1	smoke	otp_ctrl_smoke	16.410s	1.160ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.370s	227.161us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.370s	591.854us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	9.880s	5.602ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	4.790s	156.745us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	3.790s	110.481us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.370s	591.854us	20	20	100.00
		otp_ctrl_csr_aliasing	4.790s	156.745us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.670s	529.422us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.470s	543.450us	5	5	100.00
V1		TOTAL			115	116	99.14
V2	dai_access_partition_walk	otp_ctrl_partition_walk	26.930s	5.111ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.710s	3.042ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	31.510s	2.639ms	10	10	100.00
		otp_ctrl_check_fail	2.817m	40.398ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	16.330s	4.534ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	59.220s	22.466ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	49.740s	13.999ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	33.610s	13.462ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	34.900s	4.508ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.319m	25.246ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.293m	12.395ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.005m	21.023ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	8.078m	221.673ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	1.970s	562.685us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.110s	209.436us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.440s	2.668ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.440s	2.668ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.370s	227.161us	5	5	100.00
		otp_ctrl_csr_rw	2.370s	591.854us	20	20	100.00
		otp_ctrl_csr_aliasing	4.790s	156.745us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.700s	495.795us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.370s	227.161us	5	5	100.00
		otp_ctrl_csr_rw	2.370s	591.854us	20	20	100.00
		otp_ctrl_csr_aliasing	4.790s	156.745us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.700s	495.795us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	5.194m	155.298ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	5.194m	155.298ms	5	5	100.00
		otp_ctrl_tl_intg_err	21.420s	1.757ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	5.194m	155.298ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	5.194m	155.298ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	21.420s	1.757ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	16.410s	1.160ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	16.410s	1.160ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	5.194m	155.298ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	5.194m	155.298ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	5.194m	155.298ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	5.194m	155.298ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	5.194m	155.298ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	5.194m	155.298ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	5.194m	155.298ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	5.194m	155.298ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	5.194m	155.298ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	5.194m	155.298ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	5.194m	155.298ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	5.194m	155.298ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	5.194m	155.298ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	5.194m	155.298ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	5.194m	155.298ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.900s	4.508ms	200	200	100.00
		otp_ctrl_sec_cm	5.194m	155.298ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.900s	4.508ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.900s	4.508ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.900s	4.508ms	200	200	100.00
		otp_ctrl_macro_errs	1.293m	12.395ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.900s	4.508ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.900s	4.508ms	200	200	100.00
		otp_ctrl_sec_cm	5.194m	155.298ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.900s	4.508ms	200	200	100.00
		otp_ctrl_sec_cm	5.194m	155.298ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.900s	4.508ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.900s	4.508ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.900s	4.508ms	200	200	100.00
		otp_ctrl_macro_errs	1.293m	12.395ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.900s	4.508ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.900s	4.508ms	200	200	100.00
		otp_ctrl_sec_cm	5.194m	155.298ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.710s	3.042ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	2.817m	40.398ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	59.220s	22.466ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	59.220s	22.466ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	59.220s	22.466ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	59.220s	22.466ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	59.220s	22.466ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	16.410s	1.160ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	59.220s	22.466ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	16.410s	1.160ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	5.194m	155.298ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	16.330s	4.534ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	16.410s	1.160ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	16.410s	1.160ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.293m	12.395ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	14.760s	5.940ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	55.833m	437.243ms	84	100	84.00
V3		TOTAL			85	101	84.16
		TOTAL			1326	1343	98.73

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.79	93.76	96.25	95.87	90.93	97.05	96.34	93.35

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 5 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 5 failures.
  - 22.otp_ctrl_stress_all_with_rand_reset.78290992023038606118484028682463660548240945640970910760617883410570955607486
    Line 6979, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12900082164 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 12900082164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.otp_ctrl_stress_all_with_rand_reset.44099120215566578893274995616299587378812390728562195697021619663283368994174
    Line 30889, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 410592087881 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 410592087881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 4 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 4 failures.
  - 15.otp_ctrl_stress_all_with_rand_reset.56990354149723066963373253784798649151418796783062762102182593490271782707262
    Line 2268, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6058209253 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (296480806 [0x11abf026] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 6058209253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.otp_ctrl_stress_all_with_rand_reset.66757334343021985912790276295052114462024253557994064389813397221665412223756
    Line 25981, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 37735845169 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2349398196 [0x8c08f8b4] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 37735845169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
Offending '(cio_test_en_o == *)' has 4 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 3 failures.
  - 16.otp_ctrl_stress_all_with_rand_reset.56749148775307146143235592662182281710045854481592832521007220614546929403622
    Line 29195, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 18381974436 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 18381974436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 39.otp_ctrl_stress_all_with_rand_reset.42235083850766063758932171349462652461042278103211066834550203645079325187178
    Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  30460744 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  30460744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
- Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 16.otp_ctrl_csr_mem_rw_with_rand_reset.25990728632179227799934670954986026964971874223025300380166387923469004543428
    Line 267, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  26120092 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  26120092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *d* rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 4.otp_ctrl_stress_all_with_rand_reset.84473021246867929638965135788471233490577768514417858573535152368331554868620
    Line 615, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 338970257788 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 724 [0x2d4]) dai addr 2d4 rdata0 readout mismatch
  UVM_INFO @ 338970257788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=184) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 17.otp_ctrl_stress_all_with_rand_reset.75452378497060419760846969791739387497747806341665603534847809410611459306254
    Line 26299, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 802386498086 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=0xb7d2f010, Comparison=CompareOpEq, exp_data=0x0, call_count=184)
  UVM_INFO @ 802386498086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:277) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 27.otp_ctrl_stress_all_with_rand_reset.27046998866438425074407207312716737147237824162609331250893549869233227221911
    Line 29068, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 56505479997 ps: (otp_ctrl_scoreboard.sv:277) [uvm_test_top.env.scoreboard] Check failed exp_alert != OtpNoAlert (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 56505479997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:264) [otp_ctrl_background_chks_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 94.otp_ctrl_stress_all_with_rand_reset.44768654603054102946855857171360827653134838734864246981223527680379075810270
    Line 468, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/94.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 130991338206 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Timeout waiting tl_access : addr=0x16c92960
  UVM_INFO @ 130991338206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

OTP_CTRL Simulation Results

Sunday August 04 2024 23:02:21 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107130591329296133632864610148388701578652631018704528920799220771546870921898

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c8985d6745`